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cross-ppc-binutils.10414
binutils-z13-3.diff
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File binutils-z13-3.diff of Package cross-ppc-binutils.10414
commit 126b2985ce48d879c9d829b2245e4f00d05a6a74 Author: Andreas Krebbel <krebbel@linux.ibm.com> Date: Thu Jan 31 17:01:27 2019 +0100 S/390: Implement instruction set extensions opcodes/ChangeLog: 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com> Backport from mainline 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com> * s390-mkopc.c (main): Accept arch13 as cpu string. * s390-opc.c: Add new instruction formats and instruction opcode masks. * s390-opc.txt: Add new arch13 instructions. include/ChangeLog: 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com> Backport from mainline 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com> * opcode/s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_ARCH13. gas/ChangeLog: 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com> Backport from mainline 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com> * config/tc-s390.c (s390_parse_cpu): New entry for arch13. * doc/c-s390.texi: Document arch13 march option. * testsuite/gas/s390/s390.exp: Run the arch13 related tests. * testsuite/gas/s390/zarch-arch13.d: New test. * testsuite/gas/s390/zarch-arch13.s: New test. * testsuite/gas/s390/zarch-z13.d: Expect the renamed mnemonics also for z13. diff --git a/gas/config/tc-s390.c b/gas/config/tc-s390.c index 33f1c00..f74497a 100644 --- a/gas/config/tc-s390.c +++ b/gas/config/tc-s390.c @@ -290,6 +290,8 @@ s390_parse_cpu (const char * arg, { STRING_COMMA_LEN ("z13"), STRING_COMMA_LEN ("arch11"), S390_INSTR_FLAG_HTM | S390_INSTR_FLAG_VX }, { STRING_COMMA_LEN ("z14"), STRING_COMMA_LEN ("arch12"), + S390_INSTR_FLAG_HTM | S390_INSTR_FLAG_VX }, + { STRING_COMMA_LEN (""), STRING_COMMA_LEN ("arch13"), S390_INSTR_FLAG_HTM | S390_INSTR_FLAG_VX } }; static struct diff --git a/gas/doc/c-s390.texi b/gas/doc/c-s390.texi index 0b93723..27fa317 100644 --- a/gas/doc/c-s390.texi +++ b/gas/doc/c-s390.texi @@ -18,7 +18,7 @@ and eleven chip levels. The architecture modes are the Enterprise System Architecture (ESA) and the newer z/Architecture mode. The chip levels are g5 (or arch3), g6, z900 (or arch5), z990 (or arch6), z9-109, z9-ec (or arch7), z10 (or arch8), z196 (or arch9), zEC12 (or arch10), z13 -(or arch11), and z14 (or arch12). +(or arch11), z14 (or arch12), and arch13. @menu * s390 Options:: Command-line Options. @@ -68,8 +68,10 @@ are recognized: @code{z9-ec} (or @code{arch7}), @code{z10} (or @code{arch8}), @code{z196} (or @code{arch9}), -@code{zEC12} (or @code{arch10}) and -@code{z13} (or @code{arch11}). +@code{zEC12} (or @code{arch10}), +@code{z13} (or @code{arch11}), +@code{z14} (or @code{arch12}), and +@code{arch13}). Assembling an instruction that is not supported on the target processor results in an error message. diff --git a/gas/testsuite/gas/s390/s390.exp b/gas/testsuite/gas/s390/s390.exp index 3853d2f..f87a09a 100644 --- a/gas/testsuite/gas/s390/s390.exp +++ b/gas/testsuite/gas/s390/s390.exp @@ -30,6 +30,7 @@ if [expr [istarget "s390-*-*"] || [istarget "s390x-*-*"]] then { run_dump_test "zarch-zEC12" "{as -m64} {as -march=zEC12}" run_dump_test "zarch-z13" "{as -m64} {as -march=z13}" run_dump_test "zarch-arch12" "{as -m64} {as -march=arch12}" + run_dump_test "zarch-arch13" "{as -m64} {as -march=arch13}" run_dump_test "zarch-reloc" "{as -m64}" run_dump_test "zarch-operands" "{as -m64} {as -march=z9-109}" run_dump_test "zarch-machine" "{as -m64} {as -march=z900}" diff --git a/gas/testsuite/gas/s390/zarch-arch13.d b/gas/testsuite/gas/s390/zarch-arch13.d new file mode 100644 index 0000000..2530be6 --- /dev/null +++ b/gas/testsuite/gas/s390/zarch-arch13.d @@ -0,0 +1,156 @@ +#name: s390x opcode +#objdump: -dr + +.*: +file format .* + +Disassembly of section .text: + +.* <foo>: +.*: b9 f5 b0 69 [ ]*ncrk %r6,%r9,%r11 +.*: b9 e5 b0 69 [ ]*ncgrk %r6,%r9,%r11 +.*: e5 0a 6f a0 9f a0 [ ]*mvcrl 4000\(%r6\),4000\(%r9\) +.*: b9 74 b0 69 [ ]*nnrk %r6,%r9,%r11 +.*: b9 64 b0 69 [ ]*nngrk %r6,%r9,%r11 +.*: b9 76 b0 69 [ ]*nork %r6,%r9,%r11 +.*: b9 66 b0 69 [ ]*nogrk %r6,%r9,%r11 +.*: b9 77 b0 69 [ ]*nxrk %r6,%r9,%r11 +.*: b9 67 b0 69 [ ]*nxgrk %r6,%r9,%r11 +.*: b9 75 b0 69 [ ]*ocrk %r6,%r9,%r11 +.*: b9 65 b0 69 [ ]*ocgrk %r6,%r9,%r11 +.*: b9 e1 00 69 [ ]*popcnt %r6,%r9 +.*: b9 e1 d0 69 [ ]*popcnt %r6,%r9,13 +.*: b9 f0 bd 69 [ ]*selrnh %r6,%r9,%r11 +.*: b9 f0 b1 69 [ ]*selro %r6,%r9,%r11 +.*: b9 f0 b2 69 [ ]*selrh %r6,%r9,%r11 +.*: b9 f0 b2 69 [ ]*selrh %r6,%r9,%r11 +.*: b9 f0 b3 69 [ ]*selrnle %r6,%r9,%r11 +.*: b9 f0 b4 69 [ ]*selrl %r6,%r9,%r11 +.*: b9 f0 b4 69 [ ]*selrl %r6,%r9,%r11 +.*: b9 f0 b5 69 [ ]*selrnhe %r6,%r9,%r11 +.*: b9 f0 b6 69 [ ]*selrlh %r6,%r9,%r11 +.*: b9 f0 b7 69 [ ]*selrne %r6,%r9,%r11 +.*: b9 f0 b7 69 [ ]*selrne %r6,%r9,%r11 +.*: b9 f0 b8 69 [ ]*selre %r6,%r9,%r11 +.*: b9 f0 b8 69 [ ]*selre %r6,%r9,%r11 +.*: b9 f0 b9 69 [ ]*selrnlh %r6,%r9,%r11 +.*: b9 f0 ba 69 [ ]*selrhe %r6,%r9,%r11 +.*: b9 f0 bb 69 [ ]*selrnl %r6,%r9,%r11 +.*: b9 f0 bb 69 [ ]*selrnl %r6,%r9,%r11 +.*: b9 f0 bc 69 [ ]*selrle %r6,%r9,%r11 +.*: b9 f0 bd 69 [ ]*selrnh %r6,%r9,%r11 +.*: b9 f0 bd 69 [ ]*selrnh %r6,%r9,%r11 +.*: b9 f0 be 69 [ ]*selrno %r6,%r9,%r11 +.*: b9 e3 bd 69 [ ]*selgrnh %r6,%r9,%r11 +.*: b9 e3 b1 69 [ ]*selgro %r6,%r9,%r11 +.*: b9 e3 b2 69 [ ]*selgrh %r6,%r9,%r11 +.*: b9 e3 b2 69 [ ]*selgrh %r6,%r9,%r11 +.*: b9 e3 b3 69 [ ]*selgrnle %r6,%r9,%r11 +.*: b9 e3 b4 69 [ ]*selgrl %r6,%r9,%r11 +.*: b9 e3 b4 69 [ ]*selgrl %r6,%r9,%r11 +.*: b9 e3 b5 69 [ ]*selgrnhe %r6,%r9,%r11 +.*: b9 e3 b6 69 [ ]*selgrlh %r6,%r9,%r11 +.*: b9 e3 b7 69 [ ]*selgrne %r6,%r9,%r11 +.*: b9 e3 b7 69 [ ]*selgrne %r6,%r9,%r11 +.*: b9 e3 b8 69 [ ]*selgre %r6,%r9,%r11 +.*: b9 e3 b8 69 [ ]*selgre %r6,%r9,%r11 +.*: b9 e3 b9 69 [ ]*selgrnlh %r6,%r9,%r11 +.*: b9 e3 ba 69 [ ]*selgrhe %r6,%r9,%r11 +.*: b9 e3 bb 69 [ ]*selgrnl %r6,%r9,%r11 +.*: b9 e3 bb 69 [ ]*selgrnl %r6,%r9,%r11 +.*: b9 e3 bc 69 [ ]*selgrle %r6,%r9,%r11 +.*: b9 e3 bd 69 [ ]*selgrnh %r6,%r9,%r11 +.*: b9 e3 bd 69 [ ]*selgrnh %r6,%r9,%r11 +.*: b9 e3 be 69 [ ]*selgrno %r6,%r9,%r11 +.*: b9 c0 bd 69 [ ]*selhhhrnh %r6,%r9,%r11 +.*: b9 c0 b1 69 [ ]*selhhhro %r6,%r9,%r11 +.*: b9 c0 b2 69 [ ]*selhhhrh %r6,%r9,%r11 +.*: b9 c0 b2 69 [ ]*selhhhrh %r6,%r9,%r11 +.*: b9 c0 b3 69 [ ]*selhhhrnle %r6,%r9,%r11 +.*: b9 c0 b4 69 [ ]*selhhhrl %r6,%r9,%r11 +.*: b9 c0 b4 69 [ ]*selhhhrl %r6,%r9,%r11 +.*: b9 c0 b5 69 [ ]*selhhhrnhe %r6,%r9,%r11 +.*: b9 c0 b6 69 [ ]*selhhhrlh %r6,%r9,%r11 +.*: b9 c0 b7 69 [ ]*selhhhrne %r6,%r9,%r11 +.*: b9 c0 b7 69 [ ]*selhhhrne %r6,%r9,%r11 +.*: b9 c0 b8 69 [ ]*selhhhre %r6,%r9,%r11 +.*: b9 c0 b8 69 [ ]*selhhhre %r6,%r9,%r11 +.*: b9 c0 b9 69 [ ]*selhhhrnlh %r6,%r9,%r11 +.*: b9 c0 ba 69 [ ]*selhhhrhe %r6,%r9,%r11 +.*: b9 c0 bb 69 [ ]*selhhhrnl %r6,%r9,%r11 +.*: b9 c0 bb 69 [ ]*selhhhrnl %r6,%r9,%r11 +.*: b9 c0 bc 69 [ ]*selhhhrle %r6,%r9,%r11 +.*: b9 c0 bd 69 [ ]*selhhhrnh %r6,%r9,%r11 +.*: b9 c0 bd 69 [ ]*selhhhrnh %r6,%r9,%r11 +.*: b9 c0 be 69 [ ]*selhhhrno %r6,%r9,%r11 +.*: e6 f6 9f a0 d0 06 [ ]*vlbr %v15,4000\(%r6,%r9\),13 +.*: e6 f6 9f a0 10 06 [ ]*vlbrh %v15,4000\(%r6,%r9\) +.*: e6 f6 9f a0 20 06 [ ]*vlbrf %v15,4000\(%r6,%r9\) +.*: e6 f6 9f a0 30 06 [ ]*vlbrg %v15,4000\(%r6,%r9\) +.*: e6 f6 9f a0 40 06 [ ]*vlbrq %v15,4000\(%r6,%r9\) +.*: e6 f6 9f a0 d0 07 [ ]*vler %v15,4000\(%r6,%r9\),13 +.*: e6 f6 9f a0 10 07 [ ]*vlerh %v15,4000\(%r6,%r9\) +.*: e6 f6 9f a0 20 07 [ ]*vlerf %v15,4000\(%r6,%r9\) +.*: e6 f6 9f a0 30 07 [ ]*vlerg %v15,4000\(%r6,%r9\) +.*: e6 f6 9f a0 d0 04 [ ]*vllebrz %v15,4000\(%r6,%r9\),13 +.*: e6 f6 9f a0 10 04 [ ]*vllebrzh %v15,4000\(%r6,%r9\) +.*: e6 f6 9f a0 20 04 [ ]*vllebrzf %v15,4000\(%r6,%r9\) +.*: e6 f6 9f a0 30 04 [ ]*ldrv %v15,4000\(%r6,%r9\) +.*: e6 f6 9f a0 30 04 [ ]*ldrv %v15,4000\(%r6,%r9\) +.*: e6 f6 9f a0 60 04 [ ]*lerv %v15,4000\(%r6,%r9\) +.*: e6 f6 9f a0 60 04 [ ]*lerv %v15,4000\(%r6,%r9\) +.*: e6 f6 9f a0 d0 01 [ ]*vlebrh %v15,4000\(%r6,%r9\),13 +.*: e6 f6 9f a0 d0 03 [ ]*vlebrf %v15,4000\(%r6,%r9\),13 +.*: e6 f6 9f a0 d0 02 [ ]*vlebrg %v15,4000\(%r6,%r9\),13 +.*: e6 f6 9f a0 d0 05 [ ]*vlbrrep %v15,4000\(%r6,%r9\),13 +.*: e6 f6 9f a0 10 05 [ ]*vlbrreph %v15,4000\(%r6,%r9\) +.*: e6 f6 9f a0 20 05 [ ]*vlbrrepf %v15,4000\(%r6,%r9\) +.*: e6 f6 9f a0 30 05 [ ]*vlbrrepg %v15,4000\(%r6,%r9\) +.*: e6 f6 9f a0 d0 0e [ ]*vstbr %v15,4000\(%r6,%r9\),13 +.*: e6 f6 9f a0 10 0e [ ]*vstbrh %v15,4000\(%r6,%r9\) +.*: e6 f6 9f a0 20 0e [ ]*vstbrf %v15,4000\(%r6,%r9\) +.*: e6 f6 9f a0 30 0e [ ]*vstbrg %v15,4000\(%r6,%r9\) +.*: e6 f6 9f a0 40 0e [ ]*vstbrq %v15,4000\(%r6,%r9\) +.*: e6 f6 9f a0 d0 0f [ ]*vster %v15,4000\(%r6,%r9\),13 +.*: e6 f6 9f a0 10 0f [ ]*vsterh %v15,4000\(%r6,%r9\) +.*: e6 f6 9f a0 20 0f [ ]*vsterf %v15,4000\(%r6,%r9\) +.*: e6 f6 9f a0 30 0f [ ]*vsterg %v15,4000\(%r6,%r9\) +.*: e6 f6 9f a0 d0 09 [ ]*vstebrh %v15,4000\(%r6,%r9\),13 +.*: e6 f6 9f a0 d0 0b [ ]*vstebrf %v15,4000\(%r6,%r9\),13 +.*: e6 f6 9f a0 00 0b [ ]*sterv %v15,4000\(%r6,%r9\) +.*: e6 f6 9f a0 d0 0a [ ]*vstebrg %v15,4000\(%r6,%r9\),13 +.*: e6 f6 9f a0 00 0a [ ]*stdrv %v15,4000\(%r6,%r9\) +.*: e7 f1 40 fd 06 86 [ ]*vsld %v15,%v17,%v20,253 +.*: e7 f1 40 fd 06 87 [ ]*vsrd %v15,%v17,%v20,253 +.*: e7 f1 4d 00 87 8b [ ]*vstrs %v15,%v17,%v20,%v24,13 +.*: e7 f1 4d c0 87 8b [ ]*vstrs %v15,%v17,%v20,%v24,13,12 +.*: e7 f1 40 00 87 8b [ ]*vstrsb %v15,%v17,%v20,%v24 +.*: e7 f1 40 d0 87 8b [ ]*vstrsb %v15,%v17,%v20,%v24,13 +.*: e7 f1 41 00 87 8b [ ]*vstrsh %v15,%v17,%v20,%v24 +.*: e7 f1 41 d0 87 8b [ ]*vstrsh %v15,%v17,%v20,%v24,13 +.*: e7 f1 42 00 87 8b [ ]*vstrsf %v15,%v17,%v20,%v24 +.*: e7 f1 42 d0 87 8b [ ]*vstrsf %v15,%v17,%v20,%v24,13 +.*: e7 f1 40 20 87 8b [ ]*vstrszb %v15,%v17,%v20,%v24 +.*: e7 f1 40 f0 87 8b [ ]*vstrszb %v15,%v17,%v20,%v24,13 +.*: e7 f1 41 20 87 8b [ ]*vstrszh %v15,%v17,%v20,%v24 +.*: e7 f1 41 f0 87 8b [ ]*vstrszh %v15,%v17,%v20,%v24,13 +.*: e7 f1 42 20 87 8b [ ]*vstrszf %v15,%v17,%v20,%v24 +.*: e7 f1 42 f0 87 8b [ ]*vstrszf %v15,%v17,%v20,%v24,13 +.*: e7 f1 00 bc d4 c3 [ ]*vcfps %v15,%v17,13,12,11 +.*: e7 f1 00 cd 24 c3 [ ]*wcefb %v15,%v17,5,12 +.*: e7 f1 00 cd 24 c3 [ ]*wcefb %v15,%v17,5,12 +.*: e7 f1 00 bc d4 c1 [ ]*vcfpl %v15,%v17,13,12,11 +.*: e7 f1 00 cd 24 c1 [ ]*wcelfb %v15,%v17,5,12 +.*: e7 f1 00 cd 24 c1 [ ]*wcelfb %v15,%v17,5,12 +.*: e7 f1 00 bc d4 c2 [ ]*vcsfp %v15,%v17,13,12,11 +.*: e7 f1 00 cd 24 c2 [ ]*wcfeb %v15,%v17,5,12 +.*: e7 f1 00 cd 24 c2 [ ]*wcfeb %v15,%v17,5,12 +.*: e7 f1 00 bc d4 c0 [ ]*vclfp %v15,%v17,13,12,11 +.*: e7 f1 00 cd 24 c0 [ ]*wclfeb %v15,%v17,5,12 +.*: e7 f1 00 cd 24 c0 [ ]*wclfeb %v15,%v17,5,12 +.*: b9 39 b0 69 [ ]*dfltcc %r6,%r9,%r11 +.*: b9 38 00 69 [ ]*sortl %r6,%r9 +.*: e6 6f 00 d0 00 50 [ ]*vcvb %r6,%v15,13 +.*: e6 6f 00 dc 00 50 [ ]*vcvb %r6,%v15,13,12 +.*: e6 6f 00 d0 00 52 [ ]*vcvbg %r6,%v15,13 +.*: e6 6f 00 dc 00 52 [ ]*vcvbg %r6,%v15,13,12 +.*: b9 3a 00 69 [ ]*kdsa %r6,%r9 diff --git a/gas/testsuite/gas/s390/zarch-arch13.s b/gas/testsuite/gas/s390/zarch-arch13.s new file mode 100644 index 0000000..2dbbafb --- /dev/null +++ b/gas/testsuite/gas/s390/zarch-arch13.s @@ -0,0 +1,150 @@ +.text +foo: + ncrk %r6,%r9,%r11 + ncgrk %r6,%r9,%r11 + mvcrl 4000(%r6),4000(%r9) + nnrk %r6,%r9,%r11 + nngrk %r6,%r9,%r11 + nork %r6,%r9,%r11 + nogrk %r6,%r9,%r11 + nxrk %r6,%r9,%r11 + nxgrk %r6,%r9,%r11 + ocrk %r6,%r9,%r11 + ocgrk %r6,%r9,%r11 + popcnt %r6,%r9 + popcnt %r6,%r9,13 + selr %r6,%r9,%r11,13 + selro %r6,%r9,%r11 + selrh %r6,%r9,%r11 + selrp %r6,%r9,%r11 + selrnle %r6,%r9,%r11 + selrl %r6,%r9,%r11 + selrm %r6,%r9,%r11 + selrnhe %r6,%r9,%r11 + selrlh %r6,%r9,%r11 + selrne %r6,%r9,%r11 + selrnz %r6,%r9,%r11 + selre %r6,%r9,%r11 + selrz %r6,%r9,%r11 + selrnlh %r6,%r9,%r11 + selrhe %r6,%r9,%r11 + selrnl %r6,%r9,%r11 + selrnm %r6,%r9,%r11 + selrle %r6,%r9,%r11 + selrnh %r6,%r9,%r11 + selrnp %r6,%r9,%r11 + selrno %r6,%r9,%r11 + selgr %r6,%r9,%r11,13 + selgro %r6,%r9,%r11 + selgrh %r6,%r9,%r11 + selgrp %r6,%r9,%r11 + selgrnle %r6,%r9,%r11 + selgrl %r6,%r9,%r11 + selgrm %r6,%r9,%r11 + selgrnhe %r6,%r9,%r11 + selgrlh %r6,%r9,%r11 + selgrne %r6,%r9,%r11 + selgrnz %r6,%r9,%r11 + selgre %r6,%r9,%r11 + selgrz %r6,%r9,%r11 + selgrnlh %r6,%r9,%r11 + selgrhe %r6,%r9,%r11 + selgrnl %r6,%r9,%r11 + selgrnm %r6,%r9,%r11 + selgrle %r6,%r9,%r11 + selgrnh %r6,%r9,%r11 + selgrnp %r6,%r9,%r11 + selgrno %r6,%r9,%r11 + selhhhr %r6,%r9,%r11,13 + selhhhro %r6,%r9,%r11 + selhhhrh %r6,%r9,%r11 + selhhhrp %r6,%r9,%r11 + selhhhrnle %r6,%r9,%r11 + selhhhrl %r6,%r9,%r11 + selhhhrm %r6,%r9,%r11 + selhhhrnhe %r6,%r9,%r11 + selhhhrlh %r6,%r9,%r11 + selhhhrne %r6,%r9,%r11 + selhhhrnz %r6,%r9,%r11 + selhhhre %r6,%r9,%r11 + selhhhrz %r6,%r9,%r11 + selhhhrnlh %r6,%r9,%r11 + selhhhrhe %r6,%r9,%r11 + selhhhrnl %r6,%r9,%r11 + selhhhrnm %r6,%r9,%r11 + selhhhrle %r6,%r9,%r11 + selhhhrnh %r6,%r9,%r11 + selhhhrnp %r6,%r9,%r11 + selhhhrno %r6,%r9,%r11 + vlbr %v15,4000(%r6,%r9),13 + vlbrh %v15,4000(%r6,%r9) + vlbrf %v15,4000(%r6,%r9) + vlbrg %v15,4000(%r6,%r9) + vlbrq %v15,4000(%r6,%r9) + vler %v15,4000(%r6,%r9),13 + vlerh %v15,4000(%r6,%r9) + vlerf %v15,4000(%r6,%r9) + vlerg %v15,4000(%r6,%r9) + vllebrz %v15,4000(%r6,%r9),13 + vllebrzh %v15,4000(%r6,%r9) + vllebrzf %v15,4000(%r6,%r9) + ldrv %v15,4000(%r6,%r9) + vllebrzg %v15,4000(%r6,%r9) + lerv %v15,4000(%r6,%r9) + vllebrze %v15,4000(%r6,%r9) + vlebrh %v15,4000(%r6,%r9),13 + vlebrf %v15,4000(%r6,%r9),13 + vlebrg %v15,4000(%r6,%r9),13 + vlbrrep %v15,4000(%r6,%r9),13 + vlbrreph %v15,4000(%r6,%r9) + vlbrrepf %v15,4000(%r6,%r9) + vlbrrepg %v15,4000(%r6,%r9) + vstbr %v15,4000(%r6,%r9),13 + vstbrh %v15,4000(%r6,%r9) + vstbrf %v15,4000(%r6,%r9) + vstbrg %v15,4000(%r6,%r9) + vstbrq %v15,4000(%r6,%r9) + vster %v15,4000(%r6,%r9),13 + vsterh %v15,4000(%r6,%r9) + vsterf %v15,4000(%r6,%r9) + vsterg %v15,4000(%r6,%r9) + vstebrh %v15,4000(%r6,%r9),13 + vstebrf %v15,4000(%r6,%r9),13 + sterv %v15,4000(%r6,%r9) + vstebrg %v15,4000(%r6,%r9),13 + stdrv %v15,4000(%r6,%r9) + vsld %v15,%v17,%v20,253 + vsrd %v15,%v17,%v20,253 + vstrs %v15,%v17,%v20,%v24,13 + vstrs %v15,%v17,%v20,%v24,13,12 + vstrsb %v15,%v17,%v20,%v24 + vstrsb %v15,%v17,%v20,%v24,13 + vstrsh %v15,%v17,%v20,%v24 + vstrsh %v15,%v17,%v20,%v24,13 + vstrsf %v15,%v17,%v20,%v24 + vstrsf %v15,%v17,%v20,%v24,13 + vstrszb %v15,%v17,%v20,%v24 + vstrszb %v15,%v17,%v20,%v24,13 + vstrszh %v15,%v17,%v20,%v24 + vstrszh %v15,%v17,%v20,%v24,13 + vstrszf %v15,%v17,%v20,%v24 + vstrszf %v15,%v17,%v20,%v24,13 + vcfps %v15,%v17,13,12,11 + vcefb %v15,%v17,13,12 + wcefb %v15,%v17,13,12 + vcfpl %v15,%v17,13,12,11 + vcelfb %v15,%v17,13,12 + wcelfb %v15,%v17,13,12 + vcsfp %v15,%v17,13,12,11 + vcfeb %v15,%v17,13,12 + wcfeb %v15,%v17,13,12 + vclfp %v15,%v17,13,12,11 + vclfeb %v15,%v17,13,12 + wclfeb %v15,%v17,13,12 + dfltcc %r6,%r9,%r11 + sortl %r6,%r9 + vcvb %r6,%v15,13 + vcvb %r6,%v15,13,12 + vcvbg %r6,%v15,13 + vcvbg %r6,%v15,13,12 + kdsa %r6,%r9 diff --git a/gas/testsuite/gas/s390/zarch-z13.d b/gas/testsuite/gas/s390/zarch-z13.d index 434503e..e61352b 100644 --- a/gas/testsuite/gas/s390/zarch-z13.d +++ b/gas/testsuite/gas/s390/zarch-z13.d @@ -495,16 +495,16 @@ Disassembly of section .text: .*: e7 f1 40 10 36 ea [ ]*vfchedbs %v15,%v17,%v20 .*: e7 f1 40 08 36 ea [ ]*wfchedb %v15,%v17,%v20 .*: e7 f1 40 18 36 ea [ ]*wfchedbs %v15,%v17,%v20 -.*: e7 f1 00 bc d4 c3 [ ]*vcdg %v15,%v17,13,12,11 +.*: e7 f1 00 bc d4 c3 [ ]*vcfps %v15,%v17,13,12,11 .*: e7 f1 00 cd 34 c3 [ ]*wcdgb %v15,%v17,5,12 .*: e7 f1 00 cd 34 c3 [ ]*wcdgb %v15,%v17,5,12 -.*: e7 f1 00 bc d4 c1 [ ]*vcdlg %v15,%v17,13,12,11 +.*: e7 f1 00 bc d4 c1 [ ]*vcfpl %v15,%v17,13,12,11 .*: e7 f1 00 cd 34 c1 [ ]*wcdlgb %v15,%v17,5,12 .*: e7 f1 00 cd 34 c1 [ ]*wcdlgb %v15,%v17,5,12 -.*: e7 f1 00 bc d4 c2 [ ]*vcgd %v15,%v17,13,12,11 +.*: e7 f1 00 bc d4 c2 [ ]*vcsfp %v15,%v17,13,12,11 .*: e7 f1 00 cd 34 c2 [ ]*wcgdb %v15,%v17,5,12 .*: e7 f1 00 cd 34 c2 [ ]*wcgdb %v15,%v17,5,12 -.*: e7 f1 00 bc d4 c0 [ ]*vclgd %v15,%v17,13,12,11 +.*: e7 f1 00 bc d4 c0 [ ]*vclfp %v15,%v17,13,12,11 .*: e7 f1 00 cd 34 c0 [ ]*wclgdb %v15,%v17,5,12 .*: e7 f1 00 cd 34 c0 [ ]*wclgdb %v15,%v17,5,12 .*: e7 f1 40 0c d6 e5 [ ]*vfd %v15,%v17,%v20,13,12 diff --git a/include/opcode/s390.h b/include/opcode/s390.h index 400c79e..6e4faf4 100644 --- a/include/opcode/s390.h +++ b/include/opcode/s390.h @@ -43,6 +43,7 @@ enum s390_opcode_cpu_val S390_OPCODE_ZEC12, S390_OPCODE_Z13, S390_OPCODE_ARCH12, + S390_OPCODE_ARCH13, S390_OPCODE_MAXCPU }; diff --git a/opcodes/s390-mkopc.c b/opcodes/s390-mkopc.c index 1568d14..0d07678 100644 --- a/opcodes/s390-mkopc.c +++ b/opcodes/s390-mkopc.c @@ -377,6 +377,8 @@ main (void) else if (strcmp (cpu_string, "z14") == 0 || strcmp (cpu_string, "arch12") == 0) min_cpu = S390_OPCODE_ARCH12; + else if (strcmp (cpu_string, "arch13") == 0) + min_cpu = S390_OPCODE_ARCH13; else { fprintf (stderr, "Couldn't parse cpu string %s\n", cpu_string); exit (1); diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c index 40d37a9..99305d7 100644 --- a/opcodes/s390-opc.c +++ b/opcodes/s390-opc.c @@ -359,6 +359,7 @@ const struct s390_operand s390_operands[] = #define INSTR_RRF_RURR2 4, { R_24,R_16,R_28,U4_20,0,0 } /* e.g. lptea */ #define INSTR_RRF_R0RR 4, { R_24,R_16,R_28,0,0,0 } /* e.g. idte */ #define INSTR_RRF_R0RR2 4, { R_24,R_28,R_16,0,0,0 } /* e.g. ark */ +#define INSTR_RRF_R0RR3 4, { R_24,R_28,R_16,0,0,0 } /* e.g. selrz */ #define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. fidbr */ #define INSTR_RRF_U0FEFE 4, { FE_24,U4_16,FE_28,0,0,0 } /* e.g. fixbr */ #define INSTR_RRF_U0RF 4, { R_24,U4_16,F_28,0,0,0 } /* e.g. cfebr */ @@ -513,6 +514,7 @@ const struct s390_operand s390_operands[] = #define INSTR_VRR_VV0U0U 6, { V_8,V_12,U4_32,U4_24,0,0 } /* e.g. vistr */ #define INSTR_VRR_0VV0U 6, { V_12,V_16,U4_24,0,0,0 } /* e.g. vcp */ #define INSTR_VRR_RV0U 6, { R_8,V_12,U4_24,0,0,0 } /* e.g. vcvb */ +#define INSTR_VRR_RV0UU 6, { R_8,V_12,U4_24,U4_28,0,0 } /* e.g. vcvb */ #define INSTR_VSI_URDV 6, { V_32,D_20,B_16,U8_8,0,0 } /* e.g. vlrl */ #define MASK_E { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } @@ -578,6 +580,7 @@ const struct s390_operand s390_operands[] = #define MASK_RRF_RURR2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } #define MASK_RRF_R0RR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } #define MASK_RRF_R0RR2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_R0RR3 { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } #define MASK_RRF_U0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } #define MASK_RRF_U0FEFE { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } #define MASK_RRF_U0RF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } @@ -732,6 +735,7 @@ const struct s390_operand s390_operands[] = #define MASK_VRR_VV0U0U { 0xff, 0x00, 0xff, 0x0f, 0x00, 0xff } #define MASK_VRR_0VV0U { 0xff, 0xf0, 0x0f, 0x0f, 0xf0, 0xff } #define MASK_VRR_RV0U { 0xff, 0x00, 0xff, 0x0f, 0xf0, 0xff } +#define MASK_VRR_RV0UU { 0xff, 0x00, 0xff, 0x00, 0xf0, 0xff } #define MASK_VSI_URDV { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt index dd976dc..be4c97d 100644 --- a/opcodes/s390-opc.txt +++ b/opcodes/s390-opc.txt @@ -1887,3 +1887,107 @@ e70000000006 vl VRX_VRRDU "vector memory load" arch12 zarch optparm e70000000036 vlm VRS_VVRDU "vector load multiple" arch12 zarch optparm e7000000000e vst VRX_VRRDU "vector store" arch12 zarch optparm e7000000003e vstm VRS_VVRDU "vector store multiple" arch12 zarch optparm + +# arch13 instructions + +b9f5 ncrk RRF_R0RR2 " " arch13 zarch +b9e5 ncgrk RRF_R0RR2 " " arch13 zarch +e50a mvcrl SSE_RDRD " " arch13 zarch +b974 nnrk RRF_R0RR2 " " arch13 zarch +b964 nngrk RRF_R0RR2 " " arch13 zarch +b976 nork RRF_R0RR2 " " arch13 zarch +b966 nogrk RRF_R0RR2 " " arch13 zarch +b977 nxrk RRF_R0RR2 " " arch13 zarch +b967 nxgrk RRF_R0RR2 " " arch13 zarch +b975 ocrk RRF_R0RR2 " " arch13 zarch +b965 ocgrk RRF_R0RR2 " " arch13 zarch +b9e1 popcnt RRF_U0RR " " arch13 zarch optparm +b9f0 selr RRF_RURR " " arch13 zarch +b9f00000 selr*20 RRF_R0RR3 " " arch13 zarch +b9e3 selgr RRF_RURR " " arch13 zarch +b9e30000 selgr*20 RRF_R0RR3 " " arch13 zarch +b9c0 selhhhr RRF_RURR " " arch13 zarch +b9c00000 selhhhr*20 RRF_R0RR3 " " arch13 zarch + +e60000000006 vlbr VRX_VRRDU " " arch13 zarch +e60000001006 vlbrh VRX_VRRD " " arch13 zarch +e60000002006 vlbrf VRX_VRRD " " arch13 zarch +e60000003006 vlbrg VRX_VRRD " " arch13 zarch +e60000004006 vlbrq VRX_VRRD " " arch13 zarch + +e60000000007 vler VRX_VRRDU " " arch13 zarch +e60000001007 vlerh VRX_VRRD " " arch13 zarch +e60000002007 vlerf VRX_VRRD " " arch13 zarch +e60000003007 vlerg VRX_VRRD " " arch13 zarch + +e60000000004 vllebrz VRX_VRRDU " " arch13 zarch +e60000001004 vllebrzh VRX_VRRD " " arch13 zarch +e60000002004 vllebrzf VRX_VRRD " " arch13 zarch +e60000003004 ldrv VRX_VRRD " " arch13 zarch +e60000003004 vllebrzg VRX_VRRD " " arch13 zarch +e60000006004 lerv VRX_VRRD " " arch13 zarch +e60000006004 vllebrze VRX_VRRD " " arch13 zarch + +e60000000001 vlebrh VRX_VRRDU " " arch13 zarch +e60000000003 vlebrf VRX_VRRDU " " arch13 zarch +e60000000002 vlebrg VRX_VRRDU " " arch13 zarch + +e60000000005 vlbrrep VRX_VRRDU " " arch13 zarch +e60000001005 vlbrreph VRX_VRRD " " arch13 zarch +e60000002005 vlbrrepf VRX_VRRD " " arch13 zarch +e60000003005 vlbrrepg VRX_VRRD " " arch13 zarch + +e6000000000e vstbr VRX_VRRDU " " arch13 zarch +e6000000100e vstbrh VRX_VRRD " " arch13 zarch +e6000000200e vstbrf VRX_VRRD " " arch13 zarch +e6000000300e vstbrg VRX_VRRD " " arch13 zarch +e6000000400e vstbrq VRX_VRRD " " arch13 zarch + +e6000000000f vster VRX_VRRDU " " arch13 zarch +e6000000100f vsterh VRX_VRRD " " arch13 zarch +e6000000200f vsterf VRX_VRRD " " arch13 zarch +e6000000300f vsterg VRX_VRRD " " arch13 zarch + +e60000000009 vstebrh VRX_VRRDU " " arch13 zarch +e6000000000b vstebrf VRX_VRRDU " " arch13 zarch +e6000000000b sterv VRX_VRRD " " arch13 zarch +e6000000000a vstebrg VRX_VRRDU " " arch13 zarch +e6000000000a stdrv VRX_VRRD " " arch13 zarch + +e70000000086 vsld VRI_VVV0U " " arch13 zarch +e70000000087 vsrd VRI_VVV0U " " arch13 zarch + +e7000000008b vstrs VRR_VVVUU0V " " arch13 zarch optparm + +e7000000008b vstrsb VRR_VVVU0VB " " arch13 zarch optparm +e7000100008b vstrsh VRR_VVVU0VB " " arch13 zarch optparm +e7000200008b vstrsf VRR_VVVU0VB " " arch13 zarch optparm + +e7000020008b vstrszb VRR_VVVU0VB2 " " arch13 zarch optparm +e7000120008b vstrszh VRR_VVVU0VB2 " " arch13 zarch optparm +e7000220008b vstrszf VRR_VVVU0VB2 " " arch13 zarch optparm + +e700000000c3 vcfps VRR_VV0UUU " " arch13 zarch +e700000020c3 vcefb VRR_VV0UU " " arch13 zarch +e700000820c3 wcefb VRR_VV0UU8 " " arch13 zarch + +e700000000c1 vcfpl VRR_VV0UUU " " arch13 zarch +e700000020c1 vcelfb VRR_VV0UU " " arch13 zarch +e700000820c1 wcelfb VRR_VV0UU8 " " arch13 zarch + +e700000000c2 vcsfp VRR_VV0UUU " " arch13 zarch +e700000020c2 vcfeb VRR_VV0UU " " arch13 zarch +e700000820c2 wcfeb VRR_VV0UU8 " " arch13 zarch + +e700000000c0 vclfp VRR_VV0UUU " " arch13 zarch +e700000020c0 vclfeb VRR_VV0UU " " arch13 zarch +e700000820c0 wclfeb VRR_VV0UU8 " " arch13 zarch + +b939 dfltcc RRF_R0RR2 " " arch13 zarch + +b938 sortl RRE_RR " " arch13 zarch + +e60000000050 vcvb VRR_RV0UU " " arch13 zarch optparm +e60000000052 vcvbg VRR_RV0UU " " arch13 zarch optparm + +b93a kdsa RRE_RR " " arch13 zarch
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