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qemu-linux-user.8158
0094-i386-Add-bit-2-of-SPEC_CTRL-MSR-sup.patch
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File 0094-i386-Add-bit-2-of-SPEC_CTRL-MSR-sup.patch of Package qemu-linux-user.8158
From b688140cee03770cba2f90d723f6ed4f67b151dd Mon Sep 17 00:00:00 2001 From: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Date: Wed, 11 Apr 2018 17:26:51 -0400 Subject: [PATCH] i386: Add bit(2) of SPEC_CTRL MSR support - SSBD i386: Add bit(2) of SPEC_CTRL MSR support - Reduced Data Speculation Now users can do: cpu host,+spec-ctrl,+ssbd to have both IBRS and SSBD support. Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> [BR: BSC#1092885 CVE-2018-3639] Signed-off-by: Bruce Rogers <brogers@suse.com> --- target/i386/cpu.c | 2 +- target/i386/cpu.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index a97b61697e..2cbeaa25b2 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -461,7 +461,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "spec-ctrl", NULL, - NULL, NULL, NULL, NULL, + NULL, NULL, NULL, "ssbd", }, .cpuid_eax = 7, .cpuid_needs_ecx = true, .cpuid_ecx = 0, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index e0a59d78e2..395e879434 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -642,6 +642,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */ #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */ #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Speculation Control */ +#define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypass Disable */ #define CPUID_8000_0008_EBX_IBPB (1U << 12) /* Indirect Branch Prediction Barrier */
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