File nvl161673.patch of Package gcc41
You asked whether there was a smaller patch that only reordered
operands in the backend to "fix" the indexed load/store problem.
David Edelsohn does have one which I'm attaching here for you.
I just applied the patch to the latest GCC 4.1 branch and
bootstrapped it and regtested it with no problems.
* config/rs6000/rs6000.c (print_operand, 'y'): Swap position of
registers in index addresses.
(print_operand_address): Same.
Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c (revision 113054)
+++ gcc/config/rs6000/rs6000.c (working copy)
@@ -10717,12 +10717,14 @@
&& REG_P (XEXP (tmp, 0))
&& REG_P (XEXP (tmp, 1)));
- if (REGNO (XEXP (tmp, 0)) == 0)
+ /* Second index register frequently contains base address,
+ preferentially place it in rA position unless it is r0. */
+ if (REGNO (XEXP (tmp, 1)) == 0)
+ fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
+ reg_names[ REGNO (XEXP (tmp, 1)) ]);
+ else
fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
reg_names[ REGNO (XEXP (tmp, 0)) ]);
- else
- fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
- reg_names[ REGNO (XEXP (tmp, 1)) ]);
}
break;
}
@@ -10776,12 +10778,15 @@
else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
{
gcc_assert (REG_P (XEXP (x, 0)));
- if (REGNO (XEXP (x, 0)) == 0)
+
+ /* Second index register frequently contains base address,
+ preferentially place it in rA position unless it is r0. */
+ if (REGNO (XEXP (x, 1)) == 0)
+ fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
+ reg_names[ REGNO (XEXP (x, 1)) ]);
+ else
fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
reg_names[ REGNO (XEXP (x, 0)) ]);
- else
- fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
- reg_names[ REGNO (XEXP (x, 1)) ]);
}
else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",