File xf86-video-ati-ia64_screen_blank.diff of Package xorg-x11-driver-video

Index: xorg-x11-driver-video-7.4/xf86-video-ati-6.12.2/src/radeon_driver.c
===================================================================
--- xorg-x11-driver-video-7.4/xf86-video-ati-6.12.2.orig/src/radeon_driver.c
+++ xorg-x11-driver-video-7.4/xf86-video-ati-6.12.2/src/radeon_driver.c
@@ -214,6 +214,7 @@ struct RADEONInt10Save {
 	uint32_t MEMSIZE;
 	uint32_t MPP_TB_CONFIG;
         unsigned char MISC_OUT;
+        unsigned char ATTR[0x10];
 };
 
 static Bool RADEONMapMMIO(ScrnInfoPtr pScrn);
@@ -263,13 +264,67 @@ RADEONEntPtr RADEONEntPriv(ScrnInfoPtr p
     return pPriv->ptr;
 }
 
+#if !defined(__powerpc__) && !defined(__sparc__)
+/*
+ *
+ */
+void
+RADEONPreInt10SaveVGA(ScrnInfoPtr pScrn, struct RADEONInt10Save *pSave)
+{
+    IOADDRESS Base = pScrn->domainIOBase;
+    unsigned int Stat1Reg;
+    int i;
+
+    pSave->MISC_OUT = inb(pScrn->domainIOBase + RADEON_GENMO_RD);
+    Stat1Reg =  (pSave->MISC_OUT & 0x1)  ? 0x3DA : 0x3BA;
+    {
+	for (i = 0; i < 0x10; i++) {
+	    inb(Base + Stat1Reg);
+	    outb(Base + RADEON_ATTRX, i);
+	    pSave->ATTR[i] = inb(Base + RADEON_ATTRDR);
+	}
+    }
+}
+
+/*
+ *
+ */
+void
+RADEONPostInt10CheckVGA(ScrnInfoPtr pScrn, struct RADEONInt10Save *pSave)
+{
+    IOADDRESS Base = pScrn->domainIOBase;
+    unsigned int Stat1Reg =  (pSave->MISC_OUT & 0x1) ? 0x3DA : 0x3BA;
+    unsigned char CardTmp = inb(pScrn->domainIOBase + RADEON_GENMO_RD);
+    int i;
+
+    if (CardTmp != pSave->MISC_OUT) {
+	xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+		   "Restoring MiscOut (%x), setting to %x\n",
+		   CardTmp, pSave->MEM_CNTL);
+	outb(pScrn->domainIOBase + RADEON_GENMO_WT, pSave->MISC_OUT);
+    }
+
+    for (i = 0; i < 0x10; i++) {
+	inb(Base + Stat1Reg);
+	outb(Base + RADEON_ATTRX, i);
+	CardTmp = inb(Base + RADEON_ATTRDR);
+	if ( CardTmp != pSave->ATTR[i] ) {
+	    xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+		       "Restoring AttrReg[0x%i]: 0x%x to  0x%x\n",
+		       i, CardTmp, pSave->ATTR[i]);
+	    outb(Base + RADEON_ATTRDW, pSave->ATTR[i]);
+	}
+    }
+}
+#endif
+
 static void
 RADEONPreInt10Save(ScrnInfoPtr pScrn, void **pPtr)
 {
     RADEONInfoPtr  info   = RADEONPTR(pScrn);
     unsigned char *RADEONMMIO = info->MMIO;
     uint32_t       CardTmp;
-    static struct  RADEONInt10Save SaveStruct = { 0, 0, 0, 0 };
+    static struct  RADEONInt10Save SaveStruct = { 0, 0, 0, 0, {0} };
 
     if (!IS_AVIVO_VARIANT) {
 	OUTREG(0,RADEON_MEM_CNTL);
@@ -277,8 +332,9 @@ RADEONPreInt10Save(ScrnInfoPtr pScrn, vo
 	SaveStruct.MEM_CNTL = INREG(RADEON_MEM_CNTL);
 	SaveStruct.MEMSIZE = INREG(RADEON_CONFIG_MEMSIZE);
 	SaveStruct.MPP_TB_CONFIG = INREG(RADEON_MPP_TB_CONFIG);
+
 #if !defined(__powerpc__) && !defined(__sparc__)
-	SaveStruct.MISC_OUT = inb(pScrn->domainIOBase + RADEON_GENMO_RD);
+	RADEONPreInt10SaveVGA(pScrn, &SaveStruct);
 #endif
 	/*
 	 * Zap MEM_CNTL and set MPP_TB_CONFIG<31:24> to 4
@@ -342,12 +398,7 @@ RADEONPostInt10Check(ScrnInfoPtr pScrn,
 	OUTREG(RADEON_MPP_TB_CONFIG, CardTmp);
     }
 #if !defined(__powerpc__) && !defined(__sparc__)
-    if (CardTmp != pSave->MISC_OUT) {
-         xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
-		    "Restoring MiscOut (%x), setting to %x\n",
-		    CardTmp, pSave->MEM_CNTL);
-	 outb(pScrn->domainIOBase + RADEON_GENMO_WT, pSave->MISC_OUT);
-    }
+    RADEONPostInt10CheckVGA(pScrn, pSave);
 #endif
 }