File kvm-bios.patch of Package kvm.import4640

# Send to upstream BOCHS
This ACPI BIOS patch provides:
- The PCI bus definition for PIC, HPET, RTC, SMC and OSYS and SMIF
- An PBLK which provides the size of the L2 and L3 caches
- If newer hardware like ICH6 IDE is found, init it
Signed-off-by: Alex Graf - http://alex.csgraf.de
Index: qemu-kvm-0.12.2/roms/seabios-mac/src/acpi-dsdt.dsl
===================================================================
--- qemu-kvm-0.12.2.orig/roms/seabios-mac/src/acpi-dsdt.dsl
+++ qemu-kvm-0.12.2/roms/seabios-mac/src/acpi-dsdt.dsl
@@ -198,6 +198,7 @@ DefinitionBlock (
 
         Device(HPET) {
             Name(_HID,  EISAID("PNP0103"))
+            Name(_CID, 0x010CD041)
             Name(_UID, 0)
             Method (_STA, 0, NotSerialized) {
                     Return(0x0F)
@@ -214,6 +215,23 @@ DefinitionBlock (
                 )
             })
         }
+        Device (SMC)
+        {
+            Name (_HID, EisaId ("APP0001"))
+            Name (_CID, "smc-napa")
+            Name (_STA, 0x0B)
+            Name (_CRS, ResourceTemplate ()
+            {
+                IO (Decode16,
+                    0x0300,             // Range Minimum
+                    0x0300,             // Range Maximum
+                    0x01,               // Alignment
+                    0x20,               // Length
+                    )
+                IRQNoFlags ()
+                    {6}
+            })
+        }
     }
 
     Scope(\_SB.PCI0) {
Index: qemu-kvm-0.12.2/roms/seabios-mac/src/pciinit.c
===================================================================
--- qemu-kvm-0.12.2.orig/roms/seabios-mac/src/pciinit.c
+++ qemu-kvm-0.12.2/roms/seabios-mac/src/pciinit.c
@@ -18,7 +18,8 @@ static u32 pci_bios_io_addr;
 static u32 pci_bios_mem_addr;
 /* host irqs corresponding to PCI irqs A-D */
 static u8 pci_irqs[4] = {
-    10, 10, 11, 11
+//    10, 10, 11, 11
+    11, 10, 11, 10
 };
 
 static void pci_set_io_region_addr(u16 bdf, int region_num, u32 addr)
@@ -53,7 +54,9 @@ static void pci_bios_init_bridges(u16 bd
 
     if (vendor_id == PCI_VENDOR_ID_INTEL
         && (device_id == PCI_DEVICE_ID_INTEL_82371SB_0
-            || device_id == PCI_DEVICE_ID_INTEL_82371AB_0)) {
+            || device_id == PCI_DEVICE_ID_INTEL_82371AB_0
+            || device_id == PCI_DEVICE_ID_INTEL_82945GM_HB
+            || device_id == PCI_DEVICE_ID_INTEL_ICH7_1)) {
         int i, irq;
         u8 elcr[2];
 
@@ -90,7 +93,8 @@ static void pci_bios_init_device(u16 bdf
     case PCI_CLASS_STORAGE_IDE:
         if (vendor_id == PCI_VENDOR_ID_INTEL
             && (device_id == PCI_DEVICE_ID_INTEL_82371SB_1
-                || device_id == PCI_DEVICE_ID_INTEL_82371AB)) {
+                || device_id == PCI_DEVICE_ID_INTEL_82371AB
+                || device_id == PCI_DEVICE_ID_INTEL_ESB2_18)) {
             /* PIIX3/PIIX4 IDE */
             pci_config_writew(bdf, 0x40, 0x8000); // enable IDE0
             pci_config_writew(bdf, 0x42, 0x8000); // enable IDE1