File xf86-video-intel-gen6-Invalidate-texture-cache.patch of Package xorg-x11-driver-video.import4549
From 25521900df11bc71020ee80db2223f979bec5ec6 Mon Sep 17 00:00:00 2001 From: Chris Wilson <chris@chris-wilson.co.uk> Date: Thu, 7 Apr 2011 15:09:30 +0100 Subject: [PATCH] gen6: Invalidate texture cache Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> --- src/i965_reg.h | 1 + src/intel_batchbuffer.c | 1 + 2 files changed, 2 insertions(+), 0 deletions(-) diff --git a/src/i965_reg.h b/src/i965_reg.h index 3953dab..df41fba 100644 --- a/src/i965_reg.h +++ b/src/i965_reg.h @@ -169,6 +169,7 @@ #define BRW_PIPE_CONTROL_DEPTH_STALL (1 << 13) #define BRW_PIPE_CONTROL_WC_FLUSH (1 << 12) #define BRW_PIPE_CONTROL_IS_FLUSH (1 << 11) +#define BRW_PIPE_CONTROL_TC_FLUSH (1 << 10) #define BRW_PIPE_CONTROL_NOTIFY_ENABLE (1 << 8) #define BRW_PIPE_CONTROL_GLOBAL_GTT (1 << 2) #define BRW_PIPE_CONTROL_LOCAL_PGTT (0 << 2) diff --git a/src/intel_batchbuffer.c b/src/intel_batchbuffer.c index 2e1b7d9..282d8ab 100644 --- a/src/intel_batchbuffer.c +++ b/src/intel_batchbuffer.c @@ -157,6 +157,7 @@ void intel_batch_emit_flush(ScrnInfoPtr scrn) BEGIN_BATCH(4); OUT_BATCH(BRW_PIPE_CONTROL | (4 - 2)); OUT_BATCH(BRW_PIPE_CONTROL_WC_FLUSH | + BRW_PIPE_CONTROL_TC_FLUSH | BRW_PIPE_CONTROL_NOWRITE); OUT_BATCH(0); /* write address */ OUT_BATCH(0); /* write data */ -- 1.7.4.1
