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openSUSE:Evergreen:Maintenance:114
xen.openSUSE_Evergreen_11.4
CVE-2013-0153-pre2
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File CVE-2013-0153-pre2 of Package xen.openSUSE_Evergreen_11.4
Backport per-device vector map patches to xen 4.1.3 Recently we found an issue in xen 4.1. Under heavy I/O stress such as running bonnie++, Dom0 would lost its hard disk with lots of I/O errors. We found that some PCI-E devices was using the same vector as SMBus on AMD platforms and George' patch set that enables per-device vector map can fix this problem. 23752 xen: Infrastructure to allow irqs to share vector maps 23753 xen: Option to allow per-device vector maps for MSI IRQs 23754 xen: AMD IOMMU: Automatically enable per-device vector maps 23786 x86: Fix up irq vector map logic 23812 xen: Add global irq_vector_map option 23899 AMD-IOMMU: remove dead variable references From: Wei Wang2 <wei.wang2@amd.com> Committed-by: Keir Fraser <keir@xen.org> AMD-IOMMU: remove dead variable references These got orphaned up by recent changes. Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org> xen-unstable changeset: 23899:a99d75671a91 xen-unstable date: Tue Oct 04 14:11:56 2011 +0200 docs: Fix 'make docs' Signed-off-by: Keir Fraser <keir@xen.org> xen-unstable changeset: 23819:5fe770c8a8a3 xen-unstable date: Tue Sep 06 15:49:40 2011 +0100 xen: Add global irq_vector_map option, set if using AMD global intremap tables As mentioned in previous changesets, AMD IOMMU interrupt remapping tables only look at the vector, not the destination id of an interrupt. This means that all IRQs going through the same interrupt remapping table need to *not* share vectors. The irq "vector map" functionality was originally introduced after a patch which disabled global AMD IOMMUs entirely. That patch has since been reverted, meaning that AMD intremap tables can either be per-device or global. This patch therefore introduces a global irq vector map option, and enables it if we're using an AMD IOMMU with a global interrupt remapping table. This patch removes the "irq-perdev-vector-map" boolean command-line optino and replaces it with "irq_vector_map", which can have one of three values: none, global, or per-device. Setting the irq_vector_map to any value will override the default that the AMD code sets. Signed-off-by: George Dunlap <george.dunlap@eu.citrix.com> xen-unstable changeset: 23812:32814ad7458d xen-unstable date: Mon Sep 05 15:00:15 2011 +0100 x86: Fix up irq vector map logic We need to make sure that cfg->used_vector is only cleared once; otherwise there may be a race condition that allows the same vector to be assigned twice, defeating the whole purpose of the map. This makes two changes: * __clear_irq_vector() only clears the vector if the irq is not being moved * smp_iqr_move_cleanup_interrupt() only clears used_vector if this is the last place it's being used (move_cleanup_count==0 after decrement). Also make use of asserts more consistent, to catch this kind of logic bug in the future. Signed-off-by: George Dunlap <george.dunlap@eu.citrix.com> xen-unstable changeset: 23786:3a05da2dc7c0 xen-unstable date: Mon Aug 22 16:15:33 2011 +0100 xen: AMD IOMMU: Automatically enable per-device vector maps Automatically enable per-device vector maps when using IOMMU, unless disabled specifically by an IOMMU parameter. Signed-off-by: George Dunlap <george.dunlap@eu.citrix.com> xen-unstable changeset: 23754:fa4e2ca9ecff xen-unstable date: Tue Jul 26 18:37:32 2011 +0100 xen: Option to allow per-device vector maps for MSI IRQs Add a vector-map to pci_dev, and add an option to point MSI-related IRQs to the vector-map of the device. This prevents irqs from the same device from being assigned the same vector on different pcpus. This is required for systems using an AMD IOMMU, since the intremap tables on AMD only look at vector, and not destination ID. Signed-off-by: George Dunlap <george.dunlap@eu.citrix.com> xen-unstable changeset: 23753:2e0cf9428554 xen-unstable date: Tue Jul 26 18:37:16 2011 +0100 xen: Infrastructure to allow irqs to share vector maps Laying the groundwork for per-device vector maps. This generic code allows any irq to point to a vector map; all irqs sharing the same vector map will avoid sharing vectors. Signed-off-by: George Dunlap <george.dunlap@eu.citrix.com> xen-unstable changeset: 23752:ef9ed3d2aa87 xen-unstable date: Tue Jul 26 18:36:58 2011 +0100 --- a/docs/src/user.tex +++ b/docs/src/user.tex @@ -4197,6 +4197,10 @@ \item [ vcpu\_migration\_delay=$<$minimum\_time$>$] Set minimum time of vcpu migration in microseconds (default 0). This parameter avoids agressive vcpu migration. For example, the linux kernel uses 0.5ms by default. +\item [ irq\_vector\_map=xxx ] Enable irq vector non-sharing maps. Setting 'global' + will ensure that no IRQs will share vectors. Setting 'per-device' will ensure + that no IRQs from the same device will share vectors. Setting to 'none' will + disable it entirely, overriding any defaults the IOMMU code may set. \end{description} In addition, the following options may be specified on the Xen command --- a/xen/arch/x86/io_apic.c +++ b/xen/arch/x86/io_apic.c @@ -426,6 +426,13 @@ } __get_cpu_var(vector_irq)[vector] = -1; cfg->move_cleanup_count--; + + if ( cfg->move_cleanup_count == 0 + && cfg->used_vectors ) + { + ASSERT(test_bit(vector, cfg->used_vectors)); + clear_bit(vector, cfg->used_vectors); + } unlock: spin_unlock(&desc->lock); } --- a/xen/arch/x86/irq.c +++ b/xen/arch/x86/irq.c @@ -24,6 +24,8 @@ #include <asm/mach-generic/mach_apic.h> #include <public/physdev.h> +static void parse_irq_vector_map_param(char *s); + /* opt_noirqbalance: If true, software IRQ balancing/affinity is disabled. */ int __read_mostly opt_noirqbalance = 0; boolean_param("noirqbalance", opt_noirqbalance); @@ -32,6 +34,12 @@ unsigned int __read_mostly nr_irqs = 1024; integer_param("nr_irqs", nr_irqs); +/* This default may be changed by the AMD IOMMU code */ +int __read_mostly opt_irq_vector_map = OPT_IRQ_VECTOR_MAP_DEFAULT; +custom_param("irq_vector_map", parse_irq_vector_map_param); + +vmask_t global_used_vector_map; + u8 __read_mostly *irq_vector; struct irq_desc __read_mostly *irq_desc = NULL; @@ -62,6 +70,26 @@ static unsigned int __read_mostly irq_ratelimit_threshold = 10000; integer_param("irq_ratelimit", irq_ratelimit_threshold); +static void __init parse_irq_vector_map_param(char *s) +{ + char *ss; + + do { + ss = strchr(s, ','); + if ( ss ) + *ss = '\0'; + + if ( !strcmp(s, "none")) + opt_irq_vector_map=OPT_IRQ_VECTOR_MAP_NONE; + else if ( !strcmp(s, "global")) + opt_irq_vector_map=OPT_IRQ_VECTOR_MAP_GLOBAL; + else if ( !strcmp(s, "per-device")) + opt_irq_vector_map=OPT_IRQ_VECTOR_MAP_PERDEV; + + s = ss + 1; + } while ( ss ); +} + /* Must be called when irq disabled */ void lock_vector_lock(void) { @@ -97,6 +125,11 @@ cfg->vector = vector; cfg->domain = mask; irq_status[irq] = IRQ_USED; + if ( cfg->used_vectors ) + { + ASSERT(!test_bit(vector, cfg->used_vectors)); + set_bit(vector, cfg->used_vectors); + } if (IO_APIC_IRQ(irq)) irq_vector[irq] = vector; return 0; @@ -161,6 +194,7 @@ desc->depth = 1; desc->msi_desc = NULL; desc->handler = &no_irq_type; + desc->chip_data->used_vectors=NULL; cpus_setall(desc->affinity); spin_unlock_irqrestore(&desc->lock, flags); @@ -204,6 +238,12 @@ } } + if ( cfg->used_vectors ) + { + ASSERT(test_bit(vector, cfg->used_vectors)); + clear_bit(vector, cfg->used_vectors); + } + cfg->move_in_progress = 0; } @@ -263,6 +303,7 @@ cfg->vector = IRQ_VECTOR_UNASSIGNED; cpus_clear(cfg->domain); cpus_clear(cfg->old_domain); + cfg->used_vectors = NULL; } int init_irq_data(void) @@ -329,6 +370,41 @@ end_none }; +static vmask_t *irq_get_used_vector_mask(int irq) +{ + vmask_t *ret = NULL; + + if ( opt_irq_vector_map == OPT_IRQ_VECTOR_MAP_GLOBAL ) + { + struct irq_desc *desc = irq_to_desc(irq); + + ret = &global_used_vector_map; + + if ( desc->chip_data->used_vectors ) + { + printk(XENLOG_INFO "%s: Strange, unassigned irq %d already has used_vectors!\n", + __func__, irq); + } + else + { + int vector; + + vector = irq_to_vector(irq); + if ( vector > 0 ) + { + printk(XENLOG_INFO "%s: Strange, irq %d already assigned vector %d!\n", + __func__, irq, vector); + + ASSERT(!test_bit(vector, ret)); + + set_bit(vector, ret); + } + } + } + + return ret; +} + atomic_t irq_err_count; int __assign_irq_vector(int irq, struct irq_cfg *cfg, cpumask_t mask) @@ -349,6 +425,7 @@ int cpu, err; unsigned long flags; cpumask_t tmp_mask; + vmask_t *irq_used_vectors = NULL; if ((cfg->move_in_progress) || cfg->move_cleanup_count) return -EBUSY; @@ -367,6 +444,17 @@ cpus_and(mask, mask, cpu_online_map); err = -ENOSPC; + + /* This is the only place normal IRQs are ever marked + * as "in use". If they're not in use yet, check to see + * if we need to assign a global vector mask. */ + if ( irq_status[irq] == IRQ_USED ) + { + irq_used_vectors = cfg->used_vectors; + } + else + irq_used_vectors = irq_get_used_vector_mask(irq); + for_each_cpu_mask(cpu, mask) { int new_cpu; int vector, offset; @@ -389,6 +477,10 @@ if (test_bit(vector, used_vectors)) goto next; + if (irq_used_vectors + && test_bit(vector, irq_used_vectors) ) + goto next; + for_each_cpu_mask(new_cpu, tmp_mask) if (per_cpu(vector_irq, new_cpu)[vector] != -1) goto next; @@ -406,8 +498,20 @@ cpus_copy(cfg->domain, tmp_mask); irq_status[irq] = IRQ_USED; - if (IO_APIC_IRQ(irq)) - irq_vector[irq] = vector; + ASSERT((cfg->used_vectors == NULL) + || (cfg->used_vectors == irq_used_vectors)); + cfg->used_vectors = irq_used_vectors; + + if (IO_APIC_IRQ(irq)) + irq_vector[irq] = vector; + + if ( cfg->used_vectors ) + { + ASSERT(!test_bit(vector, cfg->used_vectors)); + + set_bit(vector, cfg->used_vectors); + } + err = 0; local_irq_restore(flags); break; @@ -1482,7 +1586,7 @@ if ( !IS_PRIV(current->domain) && !(IS_PRIV_FOR(current->domain, d) && - irq_access_permitted(current->domain, pirq))) + irq_access_permitted(current->domain, pirq))) return -EPERM; if ( pirq < 0 || pirq >= d->nr_pirqs || irq < 0 || irq >= nr_irqs ) @@ -1530,8 +1634,21 @@ if ( desc->handler != &no_irq_type ) dprintk(XENLOG_G_ERR, "dom%d: irq %d in use\n", - d->domain_id, irq); + d->domain_id, irq); desc->handler = &pci_msi_type; + if ( opt_irq_vector_map == OPT_IRQ_VECTOR_MAP_PERDEV + && !desc->chip_data->used_vectors ) + { + desc->chip_data->used_vectors = &pdev->info.used_vectors; + if ( desc->chip_data->vector != IRQ_VECTOR_UNASSIGNED ) + { + int vector = desc->chip_data->vector; + ASSERT(!test_bit(vector, desc->chip_data->used_vectors)); + + set_bit(vector, desc->chip_data->used_vectors); + } + } + d->arch.pirq_irq[pirq] = irq; d->arch.irq_pirq[irq] = pirq; setup_msi_irq(pdev, msi_desc, irq); @@ -1542,9 +1659,12 @@ d->arch.pirq_irq[pirq] = irq; d->arch.irq_pirq[irq] = pirq; spin_unlock_irqrestore(&desc->lock, flags); + + if ( opt_irq_vector_map == OPT_IRQ_VECTOR_MAP_PERDEV ) + printk(XENLOG_INFO "Per-device vector maps for GSIs not implemented yet.\n"); } - done: +done: return ret; } --- a/xen/drivers/passthrough/amd/pci_amd_iommu.c +++ b/xen/drivers/passthrough/amd/pci_amd_iommu.c @@ -173,6 +173,36 @@ printk("Error initialization\n"); return -ENODEV; } + + /* + * AMD IOMMUs don't distinguish between vectors destined for + * different cpus when doing interrupt remapping. This means + * that interrupts going through the same intremap table + * can't share the same vector. + * + * If irq_vector_map isn't specified, choose a sensible default: + * - If we're using per-device interemap tables, per-device + * vector non-sharing maps + * - If we're using a global interemap table, global vector + * non-sharing map + */ + if ( opt_irq_vector_map == OPT_IRQ_VECTOR_MAP_DEFAULT ) + { + if ( amd_iommu_perdev_intremap ) + { + printk("AMD-Vi: Enabling per-device vector maps\n"); + opt_irq_vector_map = OPT_IRQ_VECTOR_MAP_PERDEV; + } + else + { + printk("AMD-Vi: Enabling global vector map\n"); + opt_irq_vector_map = OPT_IRQ_VECTOR_MAP_GLOBAL; + } + } + else + { + printk("AMD-Vi: Not overriding irq_vector_map setting\n"); + } return 0; } --- a/xen/include/asm-x86/irq.h +++ b/xen/include/asm-x86/irq.h @@ -26,11 +26,14 @@ #define MAX_GSI_IRQS PAGE_SIZE * 8 #define MAX_NR_IRQS (2 * MAX_GSI_IRQS) +#include <asm/vmask.h> + struct irq_cfg { int vector; cpumask_t domain; cpumask_t old_domain; unsigned move_cleanup_count; + vmask_t *used_vectors; u8 move_in_progress : 1; }; @@ -41,6 +44,15 @@ extern u8 *irq_vector; +extern int opt_noirqbalance; + +#define OPT_IRQ_VECTOR_MAP_DEFAULT 0 /* Do the default thing */ +#define OPT_IRQ_VECTOR_MAP_NONE 1 /* None */ +#define OPT_IRQ_VECTOR_MAP_GLOBAL 2 /* One global vector map (no vector sharing) */ +#define OPT_IRQ_VECTOR_MAP_PERDEV 3 /* Per-device vetor map (no vector sharing w/in a device) */ + +extern int opt_irq_vector_map; + /* * Per-cpu current frame pointer - the location of the last exception frame on * the stack --- /dev/null +++ b/xen/include/asm-x86/vmask.h @@ -0,0 +1,10 @@ +#ifndef _ASM_VMASK_H +#define _ASM_VMASK_H + +#include <irq_vectors.h> + +typedef struct { + DECLARE_BITMAP(_bits,NR_VECTORS); +} vmask_t; + +#endif --- a/xen/include/xen/pci.h +++ b/xen/include/xen/pci.h @@ -11,6 +11,7 @@ #include <xen/types.h> #include <xen/list.h> #include <xen/spinlock.h> +#include <asm/vmask.h> #include <xen/pci_regs.h> #include <asm/page.h> @@ -42,6 +43,7 @@ u8 bus; u8 devfn; } physfn; + vmask_t used_vectors; }; struct pci_dev {
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