File ovmf-Revert-UefiCpuPkg-ArmMmuLib-Add-support-for-LPA2.patch of Package ovmf
From 0dfd6f84bfdf07dcadf45a4f5acf111b24fcf425 Mon Sep 17 00:00:00 2001
From: Richard Lyu <richard.lyu@suse.com>
Date: Wed, 25 Feb 2026 19:00:49 +0800
Subject: [PATCH] Revert "UefiCpuPkg/ArmMmuLib: Add support for LPA2"
This reverts commit 90771630bfe123de8e4bacc96f98ffe4d8308153.
---
.../Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 117 ++++--------------
1 file changed, 27 insertions(+), 90 deletions(-)
diff --git a/UefiCpuPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/UefiCpuPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c
index 568972902701..45b7c8134165 100644
--- a/UefiCpuPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c
+++ b/UefiCpuPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c
@@ -1,7 +1,7 @@
/** @file
* File managing the MMU for ARMv8 architecture
*
-* Copyright (c) 2011-2025, ARM Limited. All rights reserved.
+* Copyright (c) 2011-2020, ARM Limited. All rights reserved.
* Copyright (c) 2016, Linaro Limited. All rights reserved.
* Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
*
@@ -91,41 +91,9 @@ ArmMemoryAttributeToPageAttribute (
}
}
-// T0SZ can be below MIN_T0SZ when LPA2 is in use, meaning the page table starts at level -1
#define MIN_T0SZ 16
#define BITS_PER_LEVEL 9
-#define MAX_VA_BITS 52
-
-STATIC
-VOID
-SetOutputAddress (
- IN UINTN *Entry,
- IN UINTN Address,
- IN BOOLEAN Lpa2Enabled
- )
-{
- if (Lpa2Enabled) {
- *Entry &= ~(TT_ADDRESS_MASK_BLOCK_ENTRY_LPA2 | TT_UPPER_ADDRESS_MASK);
- *Entry |= ((UINTN)Address & TT_ADDRESS_MASK_BLOCK_ENTRY_LPA2) | (((UINTN)Address >> 50) << 8);
- } else {
- *Entry &= ~TT_ADDRESS_MASK_BLOCK_ENTRY;
- *Entry |= (Address & TT_ADDRESS_MASK_BLOCK_ENTRY);
- }
-}
-
-STATIC
-UINT64
-GetOutputAddress (
- IN UINT64 Entry,
- IN BOOLEAN Lpa2Enabled
- )
-{
- if (Lpa2Enabled) {
- return (Entry & TT_ADDRESS_MASK_BLOCK_ENTRY_LPA2) | ((Entry & TT_UPPER_ADDRESS_MASK) << (50 - 8));
- } else {
- return Entry & TT_ADDRESS_MASK_BLOCK_ENTRY;
- }
-}
+#define MAX_VA_BITS 48
STATIC
UINTN
@@ -137,12 +105,12 @@ GetRootTableEntryCount (
}
STATIC
-INTN
+UINTN
GetRootTableLevel (
IN UINTN T0SZ
)
{
- return (INTN)(T0SZ - MIN_T0SZ) / BITS_PER_LEVEL;
+ return (T0SZ - MIN_T0SZ) / BITS_PER_LEVEL;
}
STATIC
@@ -191,9 +159,8 @@ ReplaceTableEntry (
STATIC
VOID
FreePageTablesRecursive (
- IN UINT64 *TranslationTable,
- IN UINTN Level,
- IN BOOLEAN Lpa2Enabled
+ IN UINT64 *TranslationTable,
+ IN UINTN Level
)
{
UINTN Index;
@@ -204,12 +171,9 @@ FreePageTablesRecursive (
for (Index = 0; Index < TT_ENTRY_COUNT; Index++) {
if ((TranslationTable[Index] & TT_TYPE_MASK) == TT_TYPE_TABLE_ENTRY) {
FreePageTablesRecursive (
- (VOID *)GetOutputAddress (
- TranslationTable[Index],
- Lpa2Enabled
- ),
- Level + 1,
- Lpa2Enabled
+ (VOID *)(UINTN)(TranslationTable[Index] &
+ TT_ADDRESS_MASK_BLOCK_ENTRY),
+ Level + 1
);
}
}
@@ -258,10 +222,8 @@ UpdateRegionMappingRecursive (
IN UINT64 AttributeSetMask,
IN UINT64 AttributeClearMask,
IN UINT64 *PageTable,
- IN INTN Level,
- IN BOOLEAN IsRootTable,
- IN BOOLEAN TableIsLive,
- IN BOOLEAN Lpa2Enabled
+ IN UINTN Level,
+ IN BOOLEAN TableIsLive
)
{
UINTN BlockShift;
@@ -354,9 +316,7 @@ UpdateRegionMappingRecursive (
0,
TranslationTable,
Level + 1,
- FALSE,
- FALSE,
- Lpa2Enabled
+ FALSE
);
if (EFI_ERROR (Status)) {
//
@@ -371,7 +331,7 @@ UpdateRegionMappingRecursive (
NextTableIsLive = FALSE;
} else {
- TranslationTable = (VOID *)GetOutputAddress (*Entry, Lpa2Enabled);
+ TranslationTable = (VOID *)(UINTN)(*Entry & TT_ADDRESS_MASK_BLOCK_ENTRY);
NextTableIsLive = TableIsLive;
}
@@ -385,9 +345,7 @@ UpdateRegionMappingRecursive (
AttributeClearMask,
TranslationTable,
Level + 1,
- FALSE,
- NextTableIsLive,
- Lpa2Enabled
+ NextTableIsLive
);
if (EFI_ERROR (Status)) {
if (!IsTableEntry (*Entry, Level)) {
@@ -398,16 +356,14 @@ UpdateRegionMappingRecursive (
// possible for existing table entries, since we cannot revert the
// modifications we made to the subhierarchy it represents.)
//
- FreePageTablesRecursive (TranslationTable, Level + 1, Lpa2Enabled);
+ FreePageTablesRecursive (TranslationTable, Level + 1);
}
return Status;
}
if (!IsTableEntry (*Entry, Level)) {
- EntryValue = TT_TYPE_TABLE_ENTRY;
- SetOutputAddress (&EntryValue, (UINTN)TranslationTable, Lpa2Enabled);
-
+ EntryValue = (UINTN)TranslationTable | TT_TYPE_TABLE_ENTRY;
ReplaceTableEntry (
Entry,
EntryValue,
@@ -417,9 +373,8 @@ UpdateRegionMappingRecursive (
);
}
} else {
- EntryValue = (*Entry & AttributeClearMask) | AttributeSetMask;
- // Below clears shareability bits when LPA2 is in use
- SetOutputAddress (&EntryValue, RegionStart, Lpa2Enabled);
+ EntryValue = (*Entry & AttributeClearMask) | AttributeSetMask;
+ EntryValue |= RegionStart;
EntryValue |= (Level == 3) ? TT_TYPE_BLOCK_ENTRY_LEVEL3
: TT_TYPE_BLOCK_ENTRY;
@@ -438,8 +393,7 @@ UpdateRegionMapping (
IN UINT64 AttributeSetMask,
IN UINT64 AttributeClearMask,
IN UINT64 *RootTable,
- IN BOOLEAN TableIsLive,
- IN BOOLEAN Lpa2Enabled
+ IN BOOLEAN TableIsLive
)
{
UINTN T0SZ;
@@ -464,9 +418,7 @@ UpdateRegionMapping (
AttributeClearMask,
RootTable,
GetRootTableLevel (T0SZ),
- TRUE,
- TableIsLive,
- Lpa2Enabled
+ TableIsLive
);
}
@@ -474,8 +426,7 @@ STATIC
EFI_STATUS
FillTranslationTable (
IN UINT64 *RootTable,
- IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion,
- IN BOOLEAN Lpa2Enabled
+ IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion
)
{
return UpdateRegionMapping (
@@ -484,8 +435,7 @@ FillTranslationTable (
ArmMemoryAttributeToPageAttribute (MemoryRegion->Attributes) | TT_AF,
0,
RootTable,
- FALSE,
- Lpa2Enabled
+ FALSE
);
}
@@ -615,8 +565,7 @@ ArmSetMemoryAttributes (
PageAttributes,
PageAttributeMask,
ArmGetTTBR0BaseAddress (),
- TRUE,
- ArmGetTCR () & TCR_DS
+ TRUE
);
}
@@ -679,15 +628,13 @@ ArmConfigureMmu (
TCR |= TCR_PS_16TB;
} else if (MaxAddress < SIZE_256TB) {
TCR |= TCR_PS_256TB;
- } else if ((MaxAddress < SIZE_4PB) && ArmHas52BitTgran4 ()) {
- TCR |= TCR_PS_4PB | TCR_DS;
} else {
DEBUG ((
DEBUG_ERROR,
"ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n",
MaxAddress
));
- ASSERT (0); // Bigger than 48/52-bit memory space are not supported
+ ASSERT (0); // Bigger than 48-bit memory space are not supported
return EFI_UNSUPPORTED;
}
} else {
@@ -707,15 +654,13 @@ ArmConfigureMmu (
TCR |= TCR_IPS_16TB;
} else if (MaxAddress < SIZE_256TB) {
TCR |= TCR_IPS_256TB;
- } else if ((MaxAddress < SIZE_4PB) && ArmHas52BitTgran4 ()) {
- TCR |= TCR_IPS_4PB | TCR_DS;
} else {
DEBUG ((
DEBUG_ERROR,
"ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n",
MaxAddress
));
- ASSERT (0); // Bigger than 48/52-bit memory space are not supported
+ ASSERT (0); // Bigger than 48-bit memory space are not supported
return EFI_UNSUPPORTED;
}
}
@@ -764,7 +709,7 @@ ArmConfigureMmu (
ZeroMem (TranslationTable, RootTableEntryCount * sizeof (UINT64));
while (MemoryTable->Length != 0) {
- Status = FillTranslationTable (TranslationTable, MemoryTable, TCR & TCR_DS);
+ Status = FillTranslationTable (TranslationTable, MemoryTable);
if (EFI_ERROR (Status)) {
goto FreeTranslationTable;
}
@@ -785,15 +730,7 @@ ArmConfigureMmu (
MAIR_ATTR (TT_ATTR_INDX_MEMORY_WRITE_BACK, MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK)
);
- if ((TCR & TCR_IPS_MASK) == TCR_IPS_4PB) {
- ArmSetTTBR0 (
- (VOID *)
- (((UINTN)TranslationTable & 0xffffffffffc0) |
- (((UINTN)TranslationTable >> 48) << 2))
- );
- } else {
- ArmSetTTBR0 (TranslationTable);
- }
+ ArmSetTTBR0 (TranslationTable);
if (!ArmMmuEnabled ()) {
ArmDisableAlignmentCheck ();
--
2.51.0
