File pr123283.patch of Package gcc15
From 3c5b13b4058540d62282d6ad262948b82336ea7f Mon Sep 17 00:00:00 2001
From: Jeff Law <jeffrey.law@oss.qualcomm.com>
Date: Fri, 26 Dec 2025 15:24:56 -0700
Subject: [PATCH] [RISC-V][PR target/123283] Wrap naked REG operands with a
USE.
I was in the process of testing this patch when Andreas filed PR123283.
What's going on is we have patterns in sync.md which have naked operands:
(define_insn "subword_atomic_fetch_strong_<atomic_optab>"
[(set (match_operand:SI 0 "register_operand" "=&r") ;; old value at mem
(match_operand:SI 1 "memory_operand" "+A")) ;; mem location
(set (match_dup 1)
(unspec_volatile:SI
[(any_atomic:SI (match_dup 1)
(match_operand:SI 2 "arith_operand" "rI")) ;; value for op
(match_operand:SI 3 "const_int_operand")] ;; model
UNSPEC_SYNC_OLD_OP_SUBWORD))
(match_operand:SI 4 "arith_operand" "rI") ;; mask
(match_operand:SI 5 "arith_operand" "rI") ;; not_mask
(clobber (match_scratch:SI 6 "=&r")) ;; tmp_1
(clobber (match_scratch:SI 7 "=&r"))] ;; tmp_2
Note carefully operands #4 and #5 and the fact they are a toplevel construct as
opposed to being an operand of another RTX. That's a no-no. They need to be
wrapped with a USE.
I spot-checked sync.md and found a few more instances. Fixing the set I found
fixed the testsuite regressions I was seeing and also fixes the mis-compilation
of libgo. Bootstrapped and regression tested on my BPI and Pioneer. It's also
clean on the riscv64-elf and riscv32-elf targets in my tester.
PR target/123283
gcc/
* config/riscv/sync.md (subword_atomic_fetch_strong_nand): Add
USEs for naked operands that might be pseudos.
(subword_atomic_fetch_strong_<atomic_optab>): Likewise.
(subword_atomic_exchange_strong): Likewise.
(subword_atomic_cas_strong): Likewise.
---
gcc/config/riscv/sync.md | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
index 22acf0850f6..d9ff3e75f8f 100644
--- a/gcc/config/riscv/sync.md
+++ b/gcc/config/riscv/sync.md
@@ -210,8 +210,8 @@
(match_operand:SI 2 "register_operand" "rI")) ;; value for op
(match_operand:SI 3 "const_int_operand")] ;; model
UNSPEC_SYNC_OLD_OP_SUBWORD))
- (match_operand:SI 4 "register_operand" "rI") ;; mask
- (match_operand:SI 5 "register_operand" "rI") ;; not_mask
+ (use (match_operand:SI 4 "register_operand" "rI")) ;; mask
+ (use (match_operand:SI 5 "register_operand" "rI")) ;; not_mask
(clobber (match_scratch:SI 6 "=&r")) ;; tmp_1
(clobber (match_scratch:SI 7 "=&r"))] ;; tmp_2
"TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC"
@@ -277,8 +277,8 @@
(match_operand:SI 2 "register_operand" "rI"))) ;; value for op
(match_operand:SI 3 "const_int_operand")] ;; mask
UNSPEC_SYNC_OLD_OP_SUBWORD))
- (match_operand:SI 4 "register_operand" "rI") ;; mask
- (match_operand:SI 5 "register_operand" "rI") ;; not_mask
+ (use (match_operand:SI 4 "register_operand" "rI")) ;; mask
+ (use (match_operand:SI 5 "register_operand" "rI")) ;; not_mask
(clobber (match_scratch:SI 6 "=&r")) ;; tmp_1
(clobber (match_scratch:SI 7 "=&r"))] ;; tmp_2
"TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC"
@@ -488,7 +488,7 @@
[(match_operand:SI 2 "reg_or_0_operand" "rI") ;; value
(match_operand:SI 3 "const_int_operand")] ;; model
UNSPEC_SYNC_EXCHANGE_SUBWORD))
- (match_operand:SI 4 "reg_or_0_operand" "rI") ;; not_mask
+ (use (match_operand:SI 4 "reg_or_0_operand" "rI")) ;; not_mask
(clobber (match_scratch:SI 5 "=&r"))] ;; tmp_1
"TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC"
{
@@ -772,8 +772,8 @@
(match_operand:SI 3 "reg_or_0_operand" "rJ")] ;; desired value
UNSPEC_COMPARE_AND_SWAP_SUBWORD))
(match_operand:SI 4 "const_int_operand") ;; model
- (match_operand:SI 5 "register_operand" "rI") ;; mask
- (match_operand:SI 6 "register_operand" "rI") ;; not_mask
+ (use (match_operand:SI 5 "register_operand" "rI")) ;; mask
+ (use (match_operand:SI 6 "register_operand" "rI")) ;; not_mask
(clobber (match_scratch:SI 7 "=&r"))] ;; tmp_1
"TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC"
{
--
2.52.0
