File riscv.patch of Package libqt5-qtwebengine
Index: qtwebengine-everywhere-src-5.15.11/configure.pri
===================================================================
--- qtwebengine-everywhere-src-5.15.11.orig/configure.pri
+++ qtwebengine-everywhere-src-5.15.11/configure.pri
@@ -131,6 +131,7 @@ defineTest(qtConfTest_detectArch) {
contains(QT_ARCH, "arm")|contains(QT_ARCH, "arm64"): return(true)
contains(QT_ARCH, "mips"): return(true)
contains(QT_ARCH, "mips64"): return(true)
+ contains(QT_ARCH, "riscv64"): return(true)
qtLog("Architecture not supported.")
return(false)
}
Index: qtwebengine-everywhere-src-5.15.11/mkspecs/features/functions.prf
===================================================================
--- qtwebengine-everywhere-src-5.15.11.orig/mkspecs/features/functions.prf
+++ qtwebengine-everywhere-src-5.15.11/mkspecs/features/functions.prf
@@ -112,6 +112,7 @@ defineReplace(gnArch) {
contains(qtArch, "mips"): return(mipsel)
contains(qtArch, "mips64"): return(mips64el)
contains(qtArch, "mips64el"): return(mips64el)
+ contains(qtArch, "riscv64"): return(riscv64)
return(unknown)
}
Index: qtwebengine-everywhere-src-5.15.11/src/3rdparty/chromium/base/process/launch_posix.cc
===================================================================
--- qtwebengine-everywhere-src-5.15.11.orig/src/3rdparty/chromium/base/process/launch_posix.cc
+++ qtwebengine-everywhere-src-5.15.11/src/3rdparty/chromium/base/process/launch_posix.cc
@@ -704,7 +704,7 @@ NOINLINE pid_t CloneAndLongjmpInChild(un
alignas(16) char stack_buf[PTHREAD_STACK_MIN];
#if defined(ARCH_CPU_X86_FAMILY) || defined(ARCH_CPU_ARM_FAMILY) || \
defined(ARCH_CPU_MIPS_FAMILY) || defined(ARCH_CPU_S390_FAMILY) || \
- defined(ARCH_CPU_PPC64_FAMILY)
+ defined(ARCH_CPU_PPC64_FAMILY) || defined(ARCH_CPU_RISCV_FAMILY)
// The stack grows downward.
void* stack = stack_buf + sizeof(stack_buf);
#else
Index: qtwebengine-everywhere-src-5.15.11/src/3rdparty/chromium/build/build_config.h
===================================================================
--- qtwebengine-everywhere-src-5.15.11.orig/src/3rdparty/chromium/build/build_config.h
+++ qtwebengine-everywhere-src-5.15.11/src/3rdparty/chromium/build/build_config.h
@@ -193,6 +193,11 @@
#define ARCH_CPU_32_BITS 1
#define ARCH_CPU_BIG_ENDIAN 1
#endif
+#elif defined(__riscv) && __riscv_xlen == 64
+#define ARCH_CPU_RISCV_FAMILY 1
+#define ARCH_CPU_RISCV64 1
+#define ARCH_CPU_64_BITS 1
+#define ARCH_CPU_LITTLE_ENDIAN 1
#else
#error Please add support for your architecture in build/build_config.h
#endif
Index: qtwebengine-everywhere-src-5.15.11/src/3rdparty/chromium/build/toolchain/linux/BUILD.gn
===================================================================
--- qtwebengine-everywhere-src-5.15.11.orig/src/3rdparty/chromium/build/toolchain/linux/BUILD.gn
+++ qtwebengine-everywhere-src-5.15.11/src/3rdparty/chromium/build/toolchain/linux/BUILD.gn
@@ -290,3 +290,20 @@ gcc_toolchain("mips64") {
is_clang = false
}
}
+
+gcc_toolchain("riscv64") {
+ cc = "gcc"
+ cxx = "g++"
+
+ readelf = "readelf"
+ nm = "nm"
+ ar = "ar"
+ ld = cxx
+
+ toolchain_args = {
+ current_cpu = "riscv64"
+ current_os = "linux"
+ is_clang = false
+ }
+}
+
Index: qtwebengine-everywhere-src-5.15.11/src/3rdparty/chromium/skia/BUILD.gn
===================================================================
--- qtwebengine-everywhere-src-5.15.11.orig/src/3rdparty/chromium/skia/BUILD.gn
+++ qtwebengine-everywhere-src-5.15.11/src/3rdparty/chromium/skia/BUILD.gn
@@ -821,6 +821,8 @@ skia_source_set("skia_opts") {
sources = skia_opts.none_sources
} else if (current_cpu == "s390x") {
sources = skia_opts.none_sources
+ } else if (current_cpu == "riscv64") {
+ sources = skia_opts.none_sources
} else {
assert(false, "Need to port cpu specific stuff from skia_library_opts.gyp")
}
Index: qtwebengine-everywhere-src-5.15.11/src/3rdparty/chromium/third_party/angle/gni/angle.gni
===================================================================
--- qtwebengine-everywhere-src-5.15.11.orig/src/3rdparty/chromium/third_party/angle/gni/angle.gni
+++ qtwebengine-everywhere-src-5.15.11/src/3rdparty/chromium/third_party/angle/gni/angle.gni
@@ -54,7 +54,7 @@ angle_data_dir = "angledata"
declare_args() {
if (current_cpu == "arm64" || current_cpu == "x64" ||
current_cpu == "mips64el" || current_cpu == "s390x" ||
- current_cpu == "ppc64") {
+ current_cpu == "ppc64" || current_cpu == "riscv64") {
angle_64bit_current_cpu = true
} else if (current_cpu == "arm" || current_cpu == "x86" ||
current_cpu == "mipsel" || current_cpu == "s390" ||
Index: qtwebengine-everywhere-src-5.15.11/src/3rdparty/chromium/third_party/angle/include/platform/PlatformMethods.h
===================================================================
--- qtwebengine-everywhere-src-5.15.11.orig/src/3rdparty/chromium/third_party/angle/include/platform/PlatformMethods.h
+++ qtwebengine-everywhere-src-5.15.11/src/3rdparty/chromium/third_party/angle/include/platform/PlatformMethods.h
@@ -9,6 +9,7 @@
#ifndef ANGLE_PLATFORMMETHODS_H
#define ANGLE_PLATFORMMETHODS_H
+#include <stddef.h>
#include <stdint.h>
#include <stdlib.h>
#include <array>
Index: qtwebengine-everywhere-src-5.15.11/src/3rdparty/chromium/third_party/blink/renderer/platform/heap/asm/BUILD.gn
===================================================================
--- qtwebengine-everywhere-src-5.15.11.orig/src/3rdparty/chromium/third_party/blink/renderer/platform/heap/asm/BUILD.gn
+++ qtwebengine-everywhere-src-5.15.11/src/3rdparty/chromium/third_party/blink/renderer/platform/heap/asm/BUILD.gn
@@ -38,6 +38,8 @@ if (current_cpu == "x86" || current_cpu
sources = [ "SaveRegisters_mips64.S" ]
} else if (current_cpu == "ppc64") {
sources = [ "SaveRegisters_ppc64.S" ]
+ } else if (current_cpu == "riscv64") {
+ sources = [ "SaveRegisters_riscv64.S" ]
}
if (current_cpu == "arm") {
Index: qtwebengine-everywhere-src-5.15.11/src/3rdparty/chromium/third_party/blink/renderer/platform/heap/asm/SaveRegisters_riscv64.S
===================================================================
--- /dev/null
+++ qtwebengine-everywhere-src-5.15.11/src/3rdparty/chromium/third_party/blink/renderer/platform/heap/asm/SaveRegisters_riscv64.S
@@ -0,0 +1,45 @@
+/*
+ * typedef void (*PushAllRegistersCallback)(ThreadState*, intptr_t*);
+ * extern "C" void PushAllRegisters(ThreadState*, PushAllRegistersCallback)
+ */
+
+.type PushAllRegisters, %function
+.global PushAllRegisters
+.hidden PushAllRegisters
+PushAllRegisters:
+ /* Push all callee-saves registers to get them
+ * on the stack for conservative stack scanning.
+ * Reserve space for callee-saved registers and return address.
+ */
+ addi sp,sp,-112
+ /* Save the callee-saved registers and the return address. */
+ sd ra,0(sp)
+ sd s0,8(sp)
+ sd s1,16(sp)
+ sd s2,24(sp)
+ sd s3,32(sp)
+ sd s4,40(sp)
+ sd s5,48(sp)
+ sd s6,56(sp)
+ sd s7,64(sp)
+ sd s8,72(sp)
+ sd s9,80(sp)
+ sd s10,88(sp)
+ sd s11,96(sp)
+ /* Note: the callee-saved floating point registers do not need to be
+ * copied to the stack, because fp registers never hold heap pointers
+ * and so do not need to be kept visible to the garbage collector.
+ * Pass the first argument untouched in a0 and the
+ * stack pointer to the callback.
+ */
+ mv ra,a1
+ mv a1,sp
+ jalr ra
+ /* Restore return address, adjust stack and return.
+ * Note: the copied registers do not need to be reloaded here,
+ * because they were preserved by the called routine.
+ */
+ ld ra,0(sp)
+ addi sp,sp,112
+ ret
+.size PushAllRegisters, . - PushAllRegisters
Index: qtwebengine-everywhere-src-5.15.11/src/3rdparty/chromium/third_party/boringssl/src/include/openssl/base.h
===================================================================
--- qtwebengine-everywhere-src-5.15.11.orig/src/3rdparty/chromium/third_party/boringssl/src/include/openssl/base.h
+++ qtwebengine-everywhere-src-5.15.11/src/3rdparty/chromium/third_party/boringssl/src/include/openssl/base.h
@@ -105,6 +105,8 @@ extern "C" {
#elif defined(__mips__) && defined(__LP64__)
#define OPENSSL_64_BIT
#define OPENSSL_MIPS64
+#elif defined(__riscv) && __SIZEOF_POINTER__ == 8
+#define OPENSSL_64_BIT
#elif defined(__pnacl__)
#define OPENSSL_32_BIT
#define OPENSSL_PNACL
Index: qtwebengine-everywhere-src-5.15.11/src/3rdparty/chromium/third_party/dav1d/config/linux/riscv64/config.h
===================================================================
--- /dev/null
+++ qtwebengine-everywhere-src-5.15.11/src/3rdparty/chromium/third_party/dav1d/config/linux/riscv64/config.h
@@ -0,0 +1,38 @@
+/*
+ * Autogenerated by the Meson build system.
+ * Do not edit, your changes will be lost.
+ */
+
+#pragma once
+
+#define ARCH_AARCH64 0
+
+#define ARCH_ARM 0
+
+#define ARCH_PPC64LE 0
+
+#define ARCH_X86 0
+
+#define ARCH_X86_32 0
+
+#define ARCH_X86_64 0
+
+#define CONFIG_16BPC 1
+
+#define CONFIG_8BPC 1
+
+// #define CONFIG_LOG 1 -- Logging is controlled by Chromium
+
+#define ENDIANNESS_BIG 0
+
+#define HAVE_ASM 0
+
+#define HAVE_AS_FUNC 0
+
+#define HAVE_CLOCK_GETTIME 1
+
+#define HAVE_GETAUXVAL 1
+
+#define HAVE_POSIX_MEMALIGN 1
+
+#define HAVE_UNISTD_H 1
Index: qtwebengine-everywhere-src-5.15.11/src/3rdparty/chromium/third_party/lss/linux_syscall_support.h
===================================================================
--- qtwebengine-everywhere-src-5.15.11.orig/src/3rdparty/chromium/third_party/lss/linux_syscall_support.h
+++ qtwebengine-everywhere-src-5.15.11/src/3rdparty/chromium/third_party/lss/linux_syscall_support.h
@@ -88,7 +88,7 @@
*/
#if (defined(__i386__) || defined(__x86_64__) || defined(__ARM_ARCH_3__) || \
defined(__mips__) || defined(__PPC__) || defined(__ARM_EABI__) || \
- defined(__aarch64__) || defined(__s390__)) \
+ defined(__aarch64__) || defined(__s390__) || defined(__riscv)) \
&& (defined(__linux) || defined(__ANDROID__))
#ifndef SYS_CPLUSPLUS
@@ -301,7 +301,7 @@ struct kernel_old_sigaction {
} __attribute__((packed,aligned(4)));
#elif (defined(__mips__) && _MIPS_SIM == _MIPS_SIM_ABI32)
#define kernel_old_sigaction kernel_sigaction
-#elif defined(__aarch64__)
+#elif defined(__aarch64__) || defined(__riscv)
// No kernel_old_sigaction defined for arm64.
#endif
@@ -341,7 +341,9 @@ struct kernel_sigaction {
void (*sa_sigaction_)(int, siginfo_t *, void *);
};
unsigned long sa_flags;
+#ifndef __riscv
void (*sa_restorer)(void);
+#endif
struct kernel_sigset_t sa_mask;
#endif
};
@@ -519,7 +521,7 @@ struct kernel_stat {
int st_blocks;
int st_pad4[14];
};
-#elif defined(__aarch64__)
+#elif defined(__aarch64__) || defined(__riscv)
struct kernel_stat {
unsigned long st_dev;
unsigned long st_ino;
@@ -1065,7 +1067,7 @@ struct kernel_statfs {
#define __NR_getrandom (__NR_SYSCALL_BASE + 384)
#endif
/* End of ARM 3/EABI definitions */
-#elif defined(__aarch64__)
+#elif defined(__aarch64__) || defined(__riscv)
#ifndef __NR_setxattr
#define __NR_setxattr 5
#endif
@@ -1880,7 +1882,7 @@ struct kernel_statfs {
#undef LSS_RETURN
#if (defined(__i386__) || defined(__x86_64__) || defined(__ARM_ARCH_3__) \
- || defined(__ARM_EABI__) || defined(__aarch64__) || defined(__s390__))
+ || defined(__ARM_EABI__) || defined(__aarch64__) || defined(__s390__) || defined(__riscv))
/* Failing system calls return a negative result in the range of
* -1..-4095. These are "errno" values with the sign inverted.
*/
@@ -3373,6 +3375,122 @@ struct kernel_statfs {
}
LSS_RETURN(int, __ret);
}
+ #elif defined(__riscv)
+ #undef LSS_REG
+ #define LSS_REG(r,a) register int64_t __r##r __asm__("a"#r) = (int64_t)a
+ #undef LSS_BODY
+ #define LSS_BODY(type,name,args...) \
+ register int64_t __res_a0 __asm__("a0"); \
+ register int64_t __a7 __asm__("a7") = __NR_##name; \
+ int64_t __res; \
+ __asm__ __volatile__ ("scall\n" \
+ : "=r"(__res_a0) \
+ : "r"(__a7) , ## args \
+ : "memory"); \
+ __res = __res_a0; \
+ LSS_RETURN(type, __res)
+ #undef _syscall0
+ #define _syscall0(type, name) \
+ type LSS_NAME(name)(void) { \
+ LSS_BODY(type, name); \
+ }
+ #undef _syscall1
+ #define _syscall1(type, name, type1, arg1) \
+ type LSS_NAME(name)(type1 arg1) { \
+ LSS_REG(0, arg1); LSS_BODY(type, name, "r"(__r0)); \
+ }
+ #undef _syscall2
+ #define _syscall2(type, name, type1, arg1, type2, arg2) \
+ type LSS_NAME(name)(type1 arg1, type2 arg2) { \
+ LSS_REG(0, arg1); LSS_REG(1, arg2); \
+ LSS_BODY(type, name, "r"(__r0), "r"(__r1)); \
+ }
+ #undef _syscall3
+ #define _syscall3(type, name, type1, arg1, type2, arg2, type3, arg3) \
+ type LSS_NAME(name)(type1 arg1, type2 arg2, type3 arg3) { \
+ LSS_REG(0, arg1); LSS_REG(1, arg2); LSS_REG(2, arg3); \
+ LSS_BODY(type, name, "r"(__r0), "r"(__r1), "r"(__r2)); \
+ }
+ #undef _syscall4
+ #define _syscall4(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \
+ type LSS_NAME(name)(type1 arg1, type2 arg2, type3 arg3, type4 arg4) { \
+ LSS_REG(0, arg1); LSS_REG(1, arg2); LSS_REG(2, arg3); \
+ LSS_REG(3, arg4); \
+ LSS_BODY(type, name, "r"(__r0), "r"(__r1), "r"(__r2), "r"(__r3)); \
+ }
+ #undef _syscall5
+ #define _syscall5(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \
+ type5,arg5) \
+ type LSS_NAME(name)(type1 arg1, type2 arg2, type3 arg3, type4 arg4, \
+ type5 arg5) { \
+ LSS_REG(0, arg1); LSS_REG(1, arg2); LSS_REG(2, arg3); \
+ LSS_REG(3, arg4); LSS_REG(4, arg5); \
+ LSS_BODY(type, name, "r"(__r0), "r"(__r1), "r"(__r2), "r"(__r3), \
+ "r"(__r4)); \
+ }
+ #undef _syscall6
+ #define _syscall6(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \
+ type5,arg5,type6,arg6) \
+ type LSS_NAME(name)(type1 arg1, type2 arg2, type3 arg3, type4 arg4, \
+ type5 arg5, type6 arg6) { \
+ LSS_REG(0, arg1); LSS_REG(1, arg2); LSS_REG(2, arg3); \
+ LSS_REG(3, arg4); LSS_REG(4, arg5); LSS_REG(5, arg6); \
+ LSS_BODY(type, name, "r"(__r0), "r"(__r1), "r"(__r2), "r"(__r3), \
+ "r"(__r4), "r"(__r5)); \
+ }
+
+ LSS_INLINE int LSS_NAME(clone)(int (*fn)(void *), void *child_stack,
+ int flags, void *arg, int *parent_tidptr,
+ void *newtls, int *child_tidptr) {
+ int64_t __res;
+ {
+ register int64_t __res_a0 __asm__("a0");
+ register uint64_t __flags __asm__("a0") = flags;
+ register void *__stack __asm__("a1") = child_stack;
+ register void *__ptid __asm__("a2") = parent_tidptr;
+ register void *__tls __asm__("a3") = newtls;
+ register int *__ctid __asm__("a4") = child_tidptr;
+ __asm__ __volatile__(/* Push "arg" and "fn" onto the stack that will be
+ * used by the child.
+ */
+ "addi %2,%2,-16\n"
+ "sd %1, 0(%2)\n"
+ "sd %4, 8(%2)\n"
+
+ /* %a0 = syscall(%a0 = flags,
+ * %a1 = child_stack,
+ * %a2 = parent_tidptr,
+ * %a3 = newtls,
+ * %a4 = child_tidptr)
+ */
+ "li a7, %8\n"
+ "scall\n"
+
+ /* if (%a0 != 0)
+ * return %a0;
+ */
+ "bnez %0, 1f\n"
+
+ /* In the child, now. Call "fn(arg)".
+ */
+ "ld a1, 0(sp)\n"
+ "ld a0, 8(sp)\n"
+ "jalr a1\n"
+
+ /* Call _exit(%a0).
+ */
+ "li a7, %9\n"
+ "scall\n"
+ "1:\n"
+ : "=r" (__res_a0)
+ : "r"(fn), "r"(__stack), "r"(__flags), "r"(arg),
+ "r"(__ptid), "r"(__tls), "r"(__ctid),
+ "i"(__NR_clone), "i"(__NR_exit)
+ : "cc", "memory");
+ __res = __res_a0;
+ }
+ LSS_RETURN(int, __res);
+ }
#endif
#define __NR__exit __NR_exit
#define __NR__gettid __NR_gettid
@@ -4181,7 +4299,7 @@ struct kernel_statfs {
LSS_SC_BODY(4, int, 8, d, type, protocol, sv);
}
#endif
- #if defined(__ARM_EABI__) || defined (__aarch64__)
+ #if defined(__ARM_EABI__) || defined (__aarch64__) || defined(__riscv)
LSS_INLINE _syscall3(ssize_t, recvmsg, int, s, struct kernel_msghdr*, msg,
int, flags)
LSS_INLINE _syscall3(ssize_t, sendmsg, int, s, const struct kernel_msghdr*,
@@ -4503,7 +4621,7 @@ struct kernel_statfs {
// TODO: define this in an arch-independant way instead of inlining the clone
// syscall body.
-# if defined(__aarch64__)
+# if defined(__aarch64__) || defined(__riscv)
LSS_INLINE pid_t LSS_NAME(fork)(void) {
// No fork syscall on aarch64 - implement by means of the clone syscall.
// Note that this does not reset glibc's cached view of the PID/TID, so
Index: qtwebengine-everywhere-src-5.15.11/src/3rdparty/chromium/third_party/swiftshader/third_party/llvm-10.0/BUILD.gn
===================================================================
--- qtwebengine-everywhere-src-5.15.11.orig/src/3rdparty/chromium/third_party/swiftshader/third_party/llvm-10.0/BUILD.gn
+++ qtwebengine-everywhere-src-5.15.11/src/3rdparty/chromium/third_party/swiftshader/third_party/llvm-10.0/BUILD.gn
@@ -149,6 +149,7 @@ swiftshader_llvm_source_set("swiftshader
deps += [ ":swiftshader_llvm_ppc" ]
} else if (current_cpu == "x86" || current_cpu == "x64") {
deps += [ ":swiftshader_llvm_x86" ]
+ } else if (current_cpu == "riscv64") {
} else {
assert(false, "Unsupported current_cpu")
}
Index: qtwebengine-everywhere-src-5.15.11/src/3rdparty/chromium/third_party/webrtc/modules/desktop_capture/differ_block.cc
===================================================================
--- qtwebengine-everywhere-src-5.15.11.orig/src/3rdparty/chromium/third_party/webrtc/modules/desktop_capture/differ_block.cc
+++ qtwebengine-everywhere-src-5.15.11/src/3rdparty/chromium/third_party/webrtc/modules/desktop_capture/differ_block.cc
@@ -30,7 +30,7 @@ bool VectorDifference(const uint8_t* ima
static bool (*diff_proc)(const uint8_t*, const uint8_t*) = nullptr;
if (!diff_proc) {
-#if defined(WEBRTC_ARCH_ARM_FAMILY) || defined(WEBRTC_ARCH_MIPS_FAMILY)
+#if defined(WEBRTC_ARCH_ARM_FAMILY) || defined(WEBRTC_ARCH_MIPS_FAMILY) || defined(WEBRTC_ARCH_RISCV_FAMILY)
// For ARM and MIPS processors, always use C version.
// TODO(hclam): Implement a NEON version.
diff_proc = &VectorDifference_C;
Index: qtwebengine-everywhere-src-5.15.11/src/3rdparty/chromium/third_party/webrtc/rtc_base/system/arch.h
===================================================================
--- qtwebengine-everywhere-src-5.15.11.orig/src/3rdparty/chromium/third_party/webrtc/rtc_base/system/arch.h
+++ qtwebengine-everywhere-src-5.15.11/src/3rdparty/chromium/third_party/webrtc/rtc_base/system/arch.h
@@ -50,6 +50,10 @@
#elif defined(__EMSCRIPTEN__)
#define WEBRTC_ARCH_32_BITS
#define WEBRTC_ARCH_LITTLE_ENDIAN
+#elif defined(__riscv) && __riscv_xlen == 64
+#define WEBRTC_ARCH_RISCV_FAMILY
+#define WEBRTC_ARCH_64_BITS
+#define WEBRTC_ARCH_LITTLE_ENDIAN
#else
#error Please add support for your architecture in rtc_base/system/arch.h
#endif
Index: qtwebengine-everywhere-src-5.15.11/src/3rdparty/gn/tools/gn/args.cc
===================================================================
--- qtwebengine-everywhere-src-5.15.11.orig/src/3rdparty/gn/tools/gn/args.cc
+++ qtwebengine-everywhere-src-5.15.11/src/3rdparty/gn/tools/gn/args.cc
@@ -329,6 +329,7 @@ void Args::SetSystemVarsLocked(Scope* de
static const char kMips64[] = "mips64el";
static const char kS390X[] = "s390x";
static const char kPPC64[] = "ppc64";
+ static const char kRiscv64[] = "riscv64";
const char* arch = nullptr;
// Set the host CPU architecture based on the underlying OS, not
@@ -353,6 +354,8 @@ void Args::SetSystemVarsLocked(Scope* de
// This allows us to use the same toolchain as ppc64 BE
// and specific flags are included using the host_byteorder logic.
arch = kPPC64;
+ else if (os_arch == "riscv64")
+ arch = kRiscv64;
else
CHECK(false) << "OS architecture not handled. (" << os_arch << ")";
Index: qtwebengine-everywhere-src-5.15.11/src/3rdparty/gn/util/build_config.h
===================================================================
--- qtwebengine-everywhere-src-5.15.11.orig/src/3rdparty/gn/util/build_config.h
+++ qtwebengine-everywhere-src-5.15.11/src/3rdparty/gn/util/build_config.h
@@ -172,6 +172,16 @@
#define ARCH_CPU_32_BITS 1
#define ARCH_CPU_BIG_ENDIAN 1
#endif
+#elif defined(__riscv)
+#define ARCH_CPU_RISCV_FAMILY 1
+#if __riscv_xlen == 64
+#define ARCH_CPU_RISCV64 1
+#define ARCH_CPU_64_BITS 1
+#else
+#define ARCH_CPU_RISCV32 1
+#define ARCH_CPU_32_BITS 1
+#endif
+#define ARCH_CPU_LITTLE_ENDIAN 1
#else
#error Please add support for your architecture in build_config.h
#endif
