File riscv.patch of Package mvapich2

Index: mvapich2-2.3.7-1/src/mpid/ch3/channels/common/include/mv2_arch_hca_detect.h
===================================================================
--- mvapich2-2.3.7-1.orig/src/mpid/ch3/channels/common/include/mv2_arch_hca_detect.h
+++ mvapich2-2.3.7-1/src/mpid/ch3/channels/common/include/mv2_arch_hca_detect.h
@@ -229,6 +229,10 @@ typedef enum {
         MV2_ARCH_ARM_CAVIUM_V8_2S_32,
         MV2_ARCH_ARM_FUJITSU_V0_4S_48,
         MV2_ARCH_ARM_END,
+/* RISC-V Architectures */
+        MV2_ARCH_RISCV_START,
+        MV2_ARCH_RISCV_GENERIC,
+        MV2_ARCH_RISCV_END,
         MV2_ARCH_LIST_END, 
 } mv2_proc_arch_list;
 
@@ -251,6 +255,7 @@ typedef enum{
     MV2_CPU_FAMILY_AMD,
     MV2_CPU_FAMILY_POWER,
     MV2_CPU_FAMILY_ARM,
+    MV2_CPU_FAMILY_RISCV,
 }mv2_cpu_family_type;
 
 /* Multi-rail info */
Index: mvapich2-2.3.7-1/src/mpid/ch3/channels/common/include/mv2_clock.h
===================================================================
--- mvapich2-2.3.7-1.orig/src/mpid/ch3/channels/common/include/mv2_clock.h
+++ mvapich2-2.3.7-1/src/mpid/ch3/channels/common/include/mv2_clock.h
@@ -108,6 +108,14 @@ static inline cycles_t get_cycles()
     asm volatile("stck %0" : "=Q" (clk) : : "cc");
     return clk >> 2;
 }
+#elif defined(__riscv)
+typedef unsigned long cycles_t;
+static inline cycles_t get_cycles()
+{
+    unsigned long  clk;
+    asm volatile("rdtime %0" : "=r" (clk));
+    return clk;
+}
 #else
 #warning get_cycles not implemented for this architecture: attempt asm/timex.h
 #include <asm/timex.h>
Index: mvapich2-2.3.7-1/src/mpid/ch3/channels/common/src/detect/arch/mv2_arch_detect.c
===================================================================
--- mvapich2-2.3.7-1.orig/src/mpid/ch3/channels/common/src/detect/arch/mv2_arch_detect.c
+++ mvapich2-2.3.7-1/src/mpid/ch3/channels/common/src/detect/arch/mv2_arch_detect.c
@@ -252,6 +252,9 @@ static mv2_arch_types_log_t mv2_arch_typ
     {MV2_ARCH_ARM_CAVIUM_V8_2S_32,  "MV2_ARCH_ARM_CAVIUM_V8_2S_32"},
     {MV2_ARCH_ARM_FUJITSU_V0_4S_48, "MV2_ARCH_ARM_FUJITSU_V0_4S_48"},
 
+    /* RISC-V Architectures */
+    {MV2_ARCH_RISCV_GENERIC,        "MV2_ARCH_RISCV_GENERIC"},
+
     /* Unknown */
     {MV2_ARCH_UNKWN,                "MV2_ARCH_UNKWN"},
     {MV2_ARCH_LAST_ENTRY,           "MV2_ARCH_LAST_ENTRY"},
@@ -269,6 +272,7 @@ static mv2_cpu_family_types_log_t mv2_cp
     {MV2_CPU_FAMILY_AMD,   "MV2_CPU_FAMILY_AMD"},
     {MV2_CPU_FAMILY_POWER, "MV2_CPU_FAMILY_POWER"},
     {MV2_CPU_FAMILY_ARM,   "MV2_CPU_FAMILY_ARM"},
+    {MV2_CPU_FAMILY_RISCV, "MV2_CPU_FAMILY_RISCV"},
 };
 
 char *mv2_get_cpu_family_name(mv2_cpu_family_type cpu_family_type)
@@ -489,6 +493,8 @@ mv2_arch_type mv2_get_arch_type()
                 g_mv2_cpu_family_type = MV2_CPU_FAMILY_POWER;
             } else if (g_mv2_arch_type >= MV2_ARCH_ARM_START && g_mv2_arch_type <= MV2_ARCH_ARM_END) {
                 g_mv2_cpu_family_type = MV2_CPU_FAMILY_ARM;
+            } else if (g_mv2_arch_type >= MV2_ARCH_RISCV_START && g_mv2_arch_type <= MV2_ARCH_RISCV_END) {
+                g_mv2_cpu_family_type = MV2_CPU_FAMILY_RISCV;
             } else {
                 g_mv2_cpu_family_type = MV2_CPU_FAMILY_NONE;
             }
@@ -600,6 +606,13 @@ mv2_arch_type mv2_get_arch_type()
                     }
                 }
 
+                /* Identify the CPU Family for RISC-V */
+                if(! strcmp(key, "uarch")) {
+                    arch_type = MV2_ARCH_RISCV_GENERIC;
+                    g_mv2_cpu_family_type = MV2_CPU_FAMILY_RISCV;
+                    continue;
+                }
+
                 if( -1 == g_mv2_cpu_model ) {
 
                     if(! strcmp(key, MV2_STR_MODEL)) {