File iverilog.spec of Package iverilog

#
# spec file for package iverilog
#
# Copyright (c) 2020-2024 SUSE LLC
#
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# remain the property of their copyright owners, unless otherwise agreed
# upon. The license for this file, and modifications and additions to the
# file, is the same license as for the pristine package itself (unless the
# license for the pristine package is not an Open Source License, in which
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# published by the Open Source Initiative.

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Name:           iverilog
Version:        12.0
Release:        0
%define major_ver 12
Summary:        Simulation and synthesis tool for IEEE-1364
License:        GPL-2.0-or-later
Group:          Productivity/Scientific/Electronics
URL:            https://steveicarus.github.io/iverilog/
Source:         https://altushost-swe.dl.sourceforge.net/project/iverilog/iverilog/%{version}/verilog-%{version}.tar.gz
BuildRequires:  bison
BuildRequires:  fdupes
BuildRequires:  flex
BuildRequires:  gcc-c++
BuildRequires:  gperf
BuildRequires:  libbz2-devel
BuildRequires:  readline-devel
BuildRequires:  zlib-devel

%description
Icarus Verilog is a Verilog compiler that generates a variety of
engineering formats, including simulation. It strives to be true
to the IEEE-1364 standard.

%package        devel
Summary:        Icarus Verilog development files
Group:          Development/Libraries/C and C++
Requires:       %{name} = %{version}

%description    devel
This package contains necessary header files for Icarus Verilog

%prep
%setup -q -n verilog-%{version}

%build
%configure
%make_build

%install
%make_install
rm %{buildroot}/%{_libdir}/*.a
%fdupes -s %{buildroot}/%{_libdir}/ivl/

%check
make check

%files
%license COPYING
%doc README.md BUGS.txt QUICK_START.txt ieee1364-notes.txt
%doc swift.txt netlist.txt t-dll.txt vpi.txt tgt-fpga/fpga.txt
%doc cadpli/cadpli.txt xilinx-hint.txt examples
%{_bindir}/*
%{_libdir}/ivl/
%{_mandir}/man1/*

%files devel
%{_includedir}/*

%changelog