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cross-ppc-binutils
0004-S-390-Fixes-for-z13-instructions.patch
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File 0004-S-390-Fixes-for-z13-instructions.patch of Package cross-ppc-binutils
From 29983261245edabe68ab379d8e8f7691de467a57 Mon Sep 17 00:00:00 2001 From: Andreas Krebbel <krebbel@linux.vnet.ibm.com> Date: Mon, 27 Apr 2015 10:29:16 +0200 Subject: [PATCH 4/5] S/390: Fixes for z13 instructions. opcodes/ * s390-opc.c: New instruction type VV0UU2. * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK, and WFC. gas/testsuite/ * gas/s390/zarch-z13.d: Fix tests for VFCE, VLDE, VFSQ, WFK, and WFC. * gas/s390/zarch-z13.s: Likewise. # Conflicts: # gas/testsuite/ChangeLog # opcodes/ChangeLog --- gas/testsuite/gas/s390/zarch-z13.d | 10 +++++----- gas/testsuite/gas/s390/zarch-z13.s | 2 +- opcodes/s390-opc.c | 2 ++ opcodes/s390-opc.txt | 10 +++++----- 4 files changed, 13 insertions(+), 11 deletions(-) diff --git a/gas/testsuite/gas/s390/zarch-z13.d b/gas/testsuite/gas/s390/zarch-z13.d index b2e010d..66808d6 100644 --- a/gas/testsuite/gas/s390/zarch-z13.d +++ b/gas/testsuite/gas/s390/zarch-z13.d @@ -476,11 +476,11 @@ Disassembly of section .text: .*: e7 f1 40 0c d6 e3 [ ]*vfa %v15,%v17,%v20,13,12 .*: e7 f1 40 00 36 e3 [ ]*vfadb %v15,%v17,%v20 .*: e7 f1 40 08 36 e3 [ ]*wfadb %v15,%v17,%v20 -.*: e7 f1 00 cd 04 cb [ ]*wfc %v15,%v17,13,12 +.*: e7 f1 00 0c d4 cb [ ]*wfc %v15,%v17,13,12 .*: e7 f1 00 00 34 cb [ ]*wfcdb %v15,%v17 -.*: e7 f1 00 cd 04 ca [ ]*wfk %v15,%v17,13,12 +.*: e7 f1 00 0c d4 ca [ ]*wfk %v15,%v17,13,12 .*: e7 f1 00 00 34 ca [ ]*wfkdb %v15,%v17 -.*: e7 f1 40 00 06 e8 [ ]*vfce %v15,%v17,%v20 +.*: e7 f1 40 bc d6 e8 [ ]*vfce %v15,%v17,%v20,13,12,11 .*: e7 f1 40 00 36 e8 [ ]*vfcedb %v15,%v17,%v20 .*: e7 f1 40 10 36 e8 [ ]*vfcedbs %v15,%v17,%v20 .*: e7 f1 40 08 36 e8 [ ]*wfcedb %v15,%v17,%v20 @@ -513,7 +513,7 @@ Disassembly of section .text: .*: e7 f1 00 bc d4 c7 [ ]*vfi %v15,%v17,13,12,11 .*: e7 f1 00 cd 34 c7 [ ]*wfidb %v15,%v17,5,12 .*: e7 f1 00 cd 34 c7 [ ]*wfidb %v15,%v17,5,12 -.*: e7 f1 00 cd 04 c4 [ ]*vlde %v15,%v17,13,12 +.*: e7 f1 00 0c d4 c4 [ ]*vlde %v15,%v17,13,12 .*: e7 f1 00 00 24 c4 [ ]*vldeb %v15,%v17 .*: e7 f1 00 08 24 c4 [ ]*wldeb %v15,%v17 .*: e7 f1 00 bc d4 c5 [ ]*vled %v15,%v17,13,12,11 @@ -537,7 +537,7 @@ Disassembly of section .text: .*: e7 f1 00 18 34 cc [ ]*wflndb %v15,%v17 .*: e7 f1 00 20 34 cc [ ]*vflpdb %v15,%v17 .*: e7 f1 00 28 34 cc [ ]*wflpdb %v15,%v17 -.*: e7 f1 00 cd 04 ce [ ]*vfsq %v15,%v17,13,12 +.*: e7 f1 00 0c d4 ce [ ]*vfsq %v15,%v17,13,12 .*: e7 f1 00 00 34 ce [ ]*vfsqdb %v15,%v17 .*: e7 f1 00 08 34 ce [ ]*wfsqdb %v15,%v17 .*: e7 f1 40 0c d6 e2 [ ]*vfs %v15,%v17,%v20,13,12 diff --git a/gas/testsuite/gas/s390/zarch-z13.s b/gas/testsuite/gas/s390/zarch-z13.s index 688020d..c2964d8 100644 --- a/gas/testsuite/gas/s390/zarch-z13.s +++ b/gas/testsuite/gas/s390/zarch-z13.s @@ -474,7 +474,7 @@ foo: wfcdb %v15,%v17 wfk %v15,%v17,13,12 wfkdb %v15,%v17 - vfce %v15,%v17,%v20 + vfce %v15,%v17,%v20,13,12,11 vfcedb %v15,%v17,%v20 vfcedbs %v15,%v17,%v20 wfcedb %v15,%v17,%v20 diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c index 6f66fd8..9c557fa 100644 --- a/opcodes/s390-opc.c +++ b/opcodes/s390-opc.c @@ -484,6 +484,7 @@ const struct s390_operand s390_operands[] = #define INSTR_VRR_VV0U 6, { V_8,V_12,U4_32,0,0,0 } /* e.g. vseg */ #define INSTR_VRR_VV0U2 6, { V_8,V_12,U4_24,0,0,0 } /* e.g. vistrb*/ #define INSTR_VRR_VV0UU 6, { V_8,V_12,U4_28,U4_24,0,0 } /* e.g. vcdgb */ +#define INSTR_VRR_VV0UU2 6, { V_8,V_12,U4_32,U4_28,0,0 } /* e.g. wfc */ #define INSTR_VRR_VV0UU8 6, { V_8,V_12,U4_OR8_28,U4_24,0,0 } /* e.g. wcdgb */ #define INSTR_VRR_VV 6, { V_8,V_12,0,0,0,0 } /* e.g. vsegb */ #define INSTR_VRR_VVVUU0V 6, { V_8,V_12,V_16,V_32,U4_20,U4_24 } /* e.g. vstrc */ @@ -690,6 +691,7 @@ const struct s390_operand s390_operands[] = #define MASK_VRR_VV0U { 0xff, 0x00, 0xff, 0xff, 0x00, 0xff } #define MASK_VRR_VV0U2 { 0xff, 0x00, 0xff, 0x0f, 0xf0, 0xff } #define MASK_VRR_VV0UU { 0xff, 0x00, 0xff, 0x00, 0xf0, 0xff } +#define MASK_VRR_VV0UU2 { 0xff, 0x00, 0xff, 0xf0, 0x00, 0xff } #define MASK_VRR_VV0UU8 { 0xff, 0x00, 0xff, 0x08, 0xf0, 0xff } #define MASK_VRR_VV { 0xff, 0x00, 0xff, 0xff, 0xf0, 0xff } #define MASK_VRR_VVVUU0V { 0xff, 0x00, 0x00, 0x0f, 0x00, 0xff } diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt index 3429494..b86da96 100644 --- a/opcodes/s390-opc.txt +++ b/opcodes/s390-opc.txt @@ -1586,11 +1586,11 @@ e7000230008a vstrczfs VRR_VVVU0VB3 "vector string range compare word" z13 zarch e700000000e3 vfa VRR_VVV0UU "vector fp add" z13 zarch e700000030e3 vfadb VRR_VVV "vector fp add" z13 zarch e700000830e3 wfadb VRR_VVV "vector fp add" z13 zarch -e700000000cb wfc VRR_VV0UU "vector fp compare scalar" z13 zarch +e700000000cb wfc VRR_VV0UU2 "vector fp compare scalar" z13 zarch e700000030cb wfcdb VRR_VV "vector fp compare scalar" z13 zarch -e700000000ca wfk VRR_VV0UU "vector fp compare and signal scalar" z13 zarch +e700000000ca wfk VRR_VV0UU2 "vector fp compare and signal scalar" z13 zarch e700000030ca wfkdb VRR_VV "vector fp compare and signal scalar" z13 zarch -e700000000e8 vfce VRR_VVV "vector fp compare equal" z13 zarch +e700000000e8 vfce VRR_VVV0UUU "vector fp compare equal" z13 zarch e700000030e8 vfcedb VRR_VVV "vector fp compare equal" z13 zarch e700001030e8 vfcedbs VRR_VVV "vector fp compare equal" z13 zarch e700000830e8 wfcedb VRR_VVV "vector fp compare equal" z13 zarch @@ -1623,7 +1623,7 @@ e700000830e5 wfddb VRR_VVV "vector fp divide" z13 zarch e700000000c7 vfi VRR_VV0UUU "vector load fp integer" z13 zarch e700000030c7 vfidb VRR_VV0UU "vector load fp integer" z13 zarch e700000830c7 wfidb VRR_VV0UU8 "vector load fp integer" z13 zarch -e700000000c4 vlde VRR_VV0UU "vector fp load lengthened" z13 zarch +e700000000c4 vlde VRR_VV0UU2 "vector fp load lengthened" z13 zarch e700000020c4 vldeb VRR_VV "vector fp load lengthened" z13 zarch e700000820c4 wldeb VRR_VV "vector fp load lengthened" z13 zarch e700000000c5 vled VRR_VV0UUU "vector fp load rounded" z13 zarch @@ -1647,7 +1647,7 @@ e700001030cc vflndb VRR_VV "vector fp perform sign operation" z13 zarch e700001830cc wflndb VRR_VV "vector fp perform sign operation" z13 zarch e700002030cc vflpdb VRR_VV "vector fp perform sign operation" z13 zarch e700002830cc wflpdb VRR_VV "vector fp perform sign operation" z13 zarch -e700000000ce vfsq VRR_VV0UU "vector fp square root" z13 zarch +e700000000ce vfsq VRR_VV0UU2 "vector fp square root" z13 zarch e700000030ce vfsqdb VRR_VV "vector fp square root" z13 zarch e700000830ce wfsqdb VRR_VV "vector fp square root" z13 zarch e700000000e2 vfs VRR_VVV0UU "vector fp subtract" z13 zarch -- 2.3.0
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