File binutils-z13-1.diff of Package cross-spu-binutils

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File binutils-z13-1.diff of Package cross-spu-binutils

commit f47998d69f8d290564c022b010e63d5886a1fd7d
Author: Andreas Krebbel <krebbel@linux.ibm.com>
Date:   Tue Oct 23 18:02:37 2018 +0200

S/390: Support vector alignment hints
    
    This patch adds the vector alignment hints to the vector load and
    store instructions as documented in the IBM z14 Principles of
    Operations manual:
    
    http://publibfi.boulder.ibm.com/epubs/pdf/dz9zr011.pdf
    
    opcodes/ChangeLog:
    
    2018-10-23  Andreas Krebbel  <krebbel@linux.ibm.com>
    
    	* s390-opc.txt: Add vector load/store instructions with additional
    	alignment parameter.
    
    gas/ChangeLog:
    
    2018-10-23  Andreas Krebbel  <krebbel@linux.ibm.com>
    
    	* config/tc-s390.c (md_gather_operands): Fix for optional operands
    	following memory addresses.
    	* testsuite/gas/s390/zarch-arch12.d: Add regexp checks for new
    	instruction variants.
    	* testsuite/gas/s390/zarch-arch12.s: Emit new instruction
    	variants.

diff --git a/gas/config/tc-s390.c b/gas/config/tc-s390.c
index b53e33a..5a485e0 100644
--- a/gas/config/tc-s390.c
+++ b/gas/config/tc-s390.c
@@ -1510,6 +1510,21 @@ md_gather_operands (char *str,
 	  if (*str++ != ')')
 	    as_bad (_("syntax error; missing ')' after base register"));
 	  skip_optional = 0;
+
+	  if ((opcode->flags & (S390_INSTR_FLAG_OPTPARM
+				| S390_INSTR_FLAG_OPTPARM2))
+	      && opindex_ptr[1] != '\0'
+	      && opindex_ptr[2] == '\0'
+	      && *str == '\0')
+	    continue;
+
+	  if ((opcode->flags & S390_INSTR_FLAG_OPTPARM2)
+	      && opindex_ptr[1] != '\0'
+	      && opindex_ptr[2] != '\0'
+	      && opindex_ptr[3] == '\0'
+	      && *str == '\0')
+	    continue;
+
 	  /* If there is a next operand it must be separated by a comma.  */
 	  if (opindex_ptr[1] != '\0')
 	    {
diff --git a/gas/testsuite/gas/s390/zarch-arch12.d b/gas/testsuite/gas/s390/zarch-arch12.d
index 0a6796b..ac01648 100644
--- a/gas/testsuite/gas/s390/zarch-arch12.d
+++ b/gas/testsuite/gas/s390/zarch-arch12.d
@@ -201,3 +201,11 @@ Disassembly of section .text:
 .*:	b9 3c 00 69 [	 ]*prno	%r6,%r9
 .*:	b9 a1 00 69 [	 ]*tpei	%r6,%r9
 .*:	b9 ac 00 69 [	 ]*irbm	%r6,%r9
+.*:	e7 f6 9f a0 00 06 [	 ]*vl	%v15,4000\(%r6,%r9\)
+.*:	e7 f6 9f a0 d0 06 [	 ]*vl	%v15,4000\(%r6,%r9\),13
+.*:	e7 f1 6f a0 04 36 [	 ]*vlm	%v15,%v17,4000\(%r6\)
+.*:	e7 f1 6f a0 d4 36 [	 ]*vlm	%v15,%v17,4000\(%r6\),13
+.*:	e7 f6 9f a0 00 0e [	 ]*vst	%v15,4000\(%r6,%r9\)
+.*:	e7 f6 9f a0 d0 0e [	 ]*vst	%v15,4000\(%r6,%r9\),13
+.*:	e7 f1 6f a0 04 3e [	 ]*vstm	%v15,%v17,4000\(%r6\)
+.*:	e7 f1 6f a0 d4 3e [	 ]*vstm	%v15,%v17,4000\(%r6\),13
diff --git a/gas/testsuite/gas/s390/zarch-arch12.s b/gas/testsuite/gas/s390/zarch-arch12.s
index 1dd7434..51b1690 100644
--- a/gas/testsuite/gas/s390/zarch-arch12.s
+++ b/gas/testsuite/gas/s390/zarch-arch12.s
@@ -195,3 +195,11 @@ foo:
 	prno	%r6,%r9
 	tpei	%r6,%r9
 	irbm	%r6,%r9
+	vl	%v15,4000(%r6,%r9)
+	vl	%v15,4000(%r6,%r9),13
+	vlm	%v15,%v17,4000(%r6)
+	vlm	%v15,%v17,4000(%r6),13
+	vst	%v15,4000(%r6,%r9)
+	vst	%v15,4000(%r6,%r9),13
+	vstm	%v15,%v17,4000(%r6)
+	vstm	%v15,%v17,4000(%r6),13
diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt
index d8a9cce..c782aa9 100644
--- a/opcodes/s390-opc.txt
+++ b/opcodes/s390-opc.txt
@@ -1880,3 +1880,10 @@ b929 kma RRF_R0RR "cipher message with galois counter mode" arch12 zarch
 b93c prno RRE_RR "perform pseudorandom number operation" arch12 zarch
 b9a1 tpei RRE_RR "test pending external interruption" arch12 zarch
 b9ac irbm RRE_RR "insert reference bits multiple" arch12 zarch
+
+# Aligned vector store hints
+
+e70000000006 vl VRX_VRRDU "vector memory load" arch12 zarch optparm
+e70000000036 vlm VRS_VVRDU "vector load multiple" arch12 zarch optparm
+e7000000000e vst VRX_VRRDU "vector store" arch12 zarch optparm
+e7000000003e vstm VRS_VVRDU "vector store multiple" arch12 zarch optparm

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