File 6b7e7d1c-cpu-Add-Nehalem-IBRS-CPU-model.patch of Package libvirt.9596

From 6b7e7d1cc24a28a9f5ece8626f807189647d14b4 Mon Sep 17 00:00:00 2001
From: Jiri Denemark <jdenemar@redhat.com>
Date: Mon, 8 Jan 2018 20:53:25 +0100
Subject: [PATCH 06/15] cpu: Add Nehalem-IBRS CPU model

This is a variant of Nehalem with indirect branch prediction protection.
The only difference between Nehalem and Nehalem-IBRS is the added
"spec-ctrl" feature.

Thus the diff matches QEMU, but the new CPU model itself is different.
The QEMU's versions of both models contain "vme" feature, while this
feature is missing in libvirt's models. While we can't change the
existing Nehalem CPU model, we could add "vme" to Nehalem-IBRS to make
it similar to QEMU, but doing so would fool our CPU detecting code so
that any Nehalem CPU with "vme" feature would be detected as
Nehalem-IBRS CPU without spec-ctrl. Not adding "vme" to Nehalem-IBRS is
safe as QEMU will just provide the feature anyway, which matches what
happens with Nehalem (and new enough machine types).

Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Pavel Hrdina <phrdina@redhat.com>
---
 src/cpu/cpu_map.xml | 37 +++++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

Index: libvirt-3.3.0/src/cpu/cpu_map.xml
===================================================================
--- libvirt-3.3.0.orig/src/cpu/cpu_map.xml
+++ libvirt-3.3.0/src/cpu/cpu_map.xml
@@ -869,6 +869,43 @@
       <feature name='tsc'/>
     </model>
 
+    <model name='Nehalem-IBRS'>
+      <signature family='6' model='26'/>
+      <vendor name='Intel'/>
+      <feature name='apic'/>
+      <feature name='clflush'/>
+      <feature name='cmov'/>
+      <feature name='cx16'/>
+      <feature name='cx8'/>
+      <feature name='de'/>
+      <feature name='fpu'/>
+      <feature name='fxsr'/>
+      <feature name='lahf_lm'/>
+      <feature name='lm'/>
+      <feature name='mca'/>
+      <feature name='mce'/>
+      <feature name='mmx'/>
+      <feature name='msr'/>
+      <feature name='mtrr'/>
+      <feature name='nx'/>
+      <feature name='pae'/>
+      <feature name='pat'/>
+      <feature name='pge'/>
+      <feature name='pni'/>
+      <feature name='popcnt'/>
+      <feature name='pse'/>
+      <feature name='pse36'/>
+      <feature name='sep'/>
+      <feature name='spec-ctrl'/>
+      <feature name='sse'/>
+      <feature name='sse2'/>
+      <feature name='sse4.1'/>
+      <feature name='sse4.2'/>
+      <feature name='ssse3'/>
+      <feature name='syscall'/>
+      <feature name='tsc'/>
+    </model>
+
     <model name='Westmere'>
       <signature family='6' model='44'/>
       <vendor name='Intel'/>
Index: libvirt-3.3.0/src/cpu/cpu_map.c
===================================================================
--- libvirt-3.3.0.orig/src/cpu/cpu_map.c
+++ libvirt-3.3.0/src/cpu/cpu_map.c
@@ -121,8 +121,8 @@ int cpuMapLoad(const char *arch,
 
     for (element = 0; element < CPU_MAP_ELEMENT_LAST; element++) {
         if (load(ctxt, element, cb, data) < 0) {
-            virReportError(VIR_ERR_INTERNAL_ERROR,
-                           _("cannot parse CPU map for %s architecture"), arch);
+/*            virReportError(VIR_ERR_INTERNAL_ERROR,
+                           _("cannot parse CPU map for %s architecture"), arch); */
             goto cleanup;
         }
     }