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openSUSE:Leap:42.3:Update
libvirt
30b381cf-cpu-Add-SandyBridge-IBRS-CPU-model.patch
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File 30b381cf-cpu-Add-SandyBridge-IBRS-CPU-model.patch of Package libvirt
From 30b381cfdd5e92e5afa6de09f0fe533353e71d07 Mon Sep 17 00:00:00 2001 From: Jiri Denemark <jdenemar@redhat.com> Date: Mon, 8 Jan 2018 20:53:25 +0100 Subject: [PATCH 08/15] cpu: Add SandyBridge-IBRS CPU model This is a variant of SandyBridge with indirect branch prediction protection. The only difference between SandyBridge and SandyBridge-IBRS is the added "spec-ctrl" feature. The SandyBridge-IBRS model in QEMU is a bit different since SandyBridge got several additional features since we added it in cpu_map.xml: arat, vme, xsaveopt Adding them only to the -IBRS variant would confuse our CPU detection code. Signed-off-by: Jiri Denemark <jdenemar@redhat.com> Reviewed-by: Pavel Hrdina <phrdina@redhat.com> --- src/cpu/cpu_map.xml | 44 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) Index: libvirt-3.3.0/src/cpu/cpu_map.xml =================================================================== --- libvirt-3.3.0.orig/src/cpu/cpu_map.xml +++ libvirt-3.3.0/src/cpu/cpu_map.xml @@ -1024,6 +1024,50 @@ <feature name='xsave'/> </model> + <model name='SandyBridge-IBRS'> + <signature family='6' model='42'/> + <vendor name='Intel'/> + <feature name='aes'/> + <feature name='apic'/> + <feature name='avx'/> + <feature name='clflush'/> + <feature name='cmov'/> + <feature name='cx16'/> + <feature name='cx8'/> + <feature name='de'/> + <feature name='fpu'/> + <feature name='fxsr'/> + <feature name='lahf_lm'/> + <feature name='lm'/> + <feature name='mca'/> + <feature name='mce'/> + <feature name='mmx'/> + <feature name='msr'/> + <feature name='mtrr'/> + <feature name='nx'/> + <feature name='pae'/> + <feature name='pat'/> + <feature name='pclmuldq'/> + <feature name='pge'/> + <feature name='pni'/> + <feature name='popcnt'/> + <feature name='pse'/> + <feature name='pse36'/> + <feature name='rdtscp'/> + <feature name='sep'/> + <feature name='spec-ctrl'/> + <feature name='sse'/> + <feature name='sse2'/> + <feature name='sse4.1'/> + <feature name='sse4.2'/> + <feature name='ssse3'/> + <feature name='syscall'/> + <feature name='tsc'/> + <feature name='tsc-deadline'/> + <feature name='x2apic'/> + <feature name='xsave'/> + </model> + <model name='IvyBridge'> <signature family='6' model='58'/> <vendor name='Intel'/>
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