File qucs-digisim-verilog.patch of Package qucs

--- qucs-0.0.16.orig/qucs/components/digi_sim.cpp	2011-03-03 19:14:14.000000000 +0300
+++ qucs-0.0.16/qucs/components/digi_sim.cpp	2012-09-29 12:38:03.307892869 +0400
@@ -45,7 +45,7 @@
 	QObject::tr("type of simulation")+" [TruthTable, TimeList]"));
   Props.append(new Property("time", "10 ns", false,
 	QObject::tr("duration of TimeList simulation")));
-  Props.append(new Property("Model", "VHDL", false,
+  Props.append(new Property("Model", "Verilog", false,
 	QObject::tr("netlist format")+" [VHDL, Verilog]"));
 }