File 26235-IOMMU-ATS-max-queue-depth.patch of Package xen.openSUSE_12.1_Update

# HG changeset patch
# User Jan Beulich <jbeulich@suse.com>
# Date 1354697534 -3600
# Node ID 670b07e8d7382229639af0d1df30071e6c1ebb19
# Parent  bc624b00d6d601f00a53c2f7502a82dcef60f882
IOMMU/ATS: fix maximum queue depth calculation

The capabilities register field is a 5-bit value, and the 5 bits all
being zero actually means 32 entries.

Under the assumption that amd_iommu_flush_iotlb() really just tried
to correct for the miscalculation above when adding 32 to the value,
that adjustment is also being removed.

Signed-off-by: Jan Beulich <jbeulich@suse.com>
Acked-by Xiantao Zhang <xiantao.zhang@intel.com>
Acked-by: Wei Huang <wei.huang2@amd.com>

--- a/xen/drivers/passthrough/vtd/x86/ats.c
+++ b/xen/drivers/passthrough/vtd/x86/ats.c
@@ -32,7 +32,7 @@ static LIST_HEAD(ats_dev_drhd_units);
 
 #define ATS_REG_CAP    4
 #define ATS_REG_CTL    6
-#define ATS_QUEUE_DEPTH_MASK     0xF
+#define ATS_QUEUE_DEPTH_MASK     0x1f
 #define ATS_ENABLE               (1<<15)
 
 struct pci_ats_dev {
@@ -178,7 +178,8 @@ int enable_ats_device(int seg, int bus, 
         pdev->devfn = devfn;
         value = pci_conf_read16(bus, PCI_SLOT(devfn),
                                 PCI_FUNC(devfn), pos + ATS_REG_CAP);
-        pdev->ats_queue_depth = value & ATS_QUEUE_DEPTH_MASK;
+        pdev->ats_queue_depth = value & ATS_QUEUE_DEPTH_MASK ?:
+                                ATS_QUEUE_DEPTH_MASK + 1;
         list_add(&pdev->list, &ats_devices);
     }