File 26660-x86-fix-CMCI-injection.patch of Package xen.openSUSE_12.1_Update

# Commit 2f8c55ccefe49bb526df0eaf5fa9b7b788422208
# Date 2013-02-26 10:15:56 +0100
# Author Jan Beulich <jbeulich@suse.com>
# Committer Jan Beulich <jbeulich@suse.com>
x86: fix CMCI injection

This fixes the wrong use of literal vector 0xF7 with an "int"
instruction (invalidated by 25113:14609be41f36) and the fact that doing
the injection via a software interrupt was never valid anyway (because
cmci_interrupt() acks the LAPIC, which does the wrong thing if the
interrupt didn't get delivered though it).

In order to do latter, the patch introduces send_IPI_self(), at once
removing two opend coded uses of "genapic" in the IRQ handling code.

Reported-by: Yongjie Ren <yongjie.ren@intel.com>
Signed-off-by: Jan Beulich <jbeulich@suse.com>
Tested-by: Yongjie Ren <yongjie.ren@intel.com>
Acked-by: Keir Fraser <keir@xen.org>

--- a/xen/arch/x86/cpu/mcheck/mce.c
+++ b/xen/arch/x86/cpu/mcheck/mce.c
@@ -1251,12 +1251,6 @@ static void x86_mc_mceinject(void *data)
     __asm__ __volatile__("int $0x12");
 }
 
-static void x86_cmci_inject(void *data)
-{
-    printk("Simulating CMCI on cpu %d\n", smp_processor_id());
-    __asm__ __volatile__("int $0xf7");
-}
-
 #if BITS_PER_LONG == 64
 
 #define ID2COOKIE(id) ((mctelem_cookie_t)(id))
@@ -1539,7 +1533,9 @@ long do_mca(XEN_GUEST_HANDLE(xen_mc_t) u
             if ( !cmci_support )
                 return x86_mcerr(
                     "No CMCI supported in platform\n", -EINVAL);
-            on_selected_cpus(&cpumap, x86_cmci_inject, NULL, 1);
+            if ( cpu_isset(smp_processor_id(), cpumap) )
+                send_IPI_self(CMCI_APIC_VECTOR);
+            send_IPI_mask(&cpumap, CMCI_APIC_VECTOR);
             break;
         default:
             return x86_mcerr("Wrong mca type\n", -EINVAL);
--- a/xen/arch/x86/io_apic.c
+++ b/xen/arch/x86/io_apic.c
@@ -551,7 +551,7 @@ fastcall void smp_irq_move_cleanup_inter
          * to myself.
          */
         if (irr  & (1 << (vector % 32))) {
-            genapic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
+            send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
             goto unlock;
         }
         __get_cpu_var(vector_irq)[vector] = -1;
@@ -577,7 +577,7 @@ static void send_cleanup_vector(struct i
 
     cpus_and(cleanup_mask, cfg->old_cpu_mask, cpu_online_map);
     cfg->move_cleanup_count = cpus_weight(cleanup_mask);
-    genapic->send_IPI_mask(&cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
+    send_IPI_mask(&cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
 
     cfg->move_in_progress = 0;
 }
--- a/xen/arch/x86/smp.c
+++ b/xen/arch/x86/smp.c
@@ -43,6 +43,11 @@ void send_IPI_mask(const cpumask_t *mask
     genapic->send_IPI_mask(mask, vector);
 }
 
+void send_IPI_self(int vector)
+{
+    genapic->send_IPI_self(vector);
+}
+
 /*
  *	Some notes on x86 processor bugs affecting SMP operation:
  *
--- a/xen/include/asm-x86/smp.h
+++ b/xen/include/asm-x86/smp.h
@@ -30,7 +30,8 @@ DECLARE_PER_CPU(cpumask_t, cpu_core_map)
 
 void smp_send_nmi_allbutself(void);
 
-void  send_IPI_mask(const cpumask_t *mask, int vector);
+void send_IPI_mask(const cpumask_t *, int vector);
+void send_IPI_self(int vector);
 
 extern void (*mtrr_hook) (void);