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Yosys open synthesis suite

Yosys is a synthesis suite for FPGAs and ASICs.
It includes a verilog parser and the logic synthetizer ABC.

Source Files (show merged sources derived from linked package)

Filename Size Changed Actions
0001-Avoid-symbol-reference-from-library-to-hosting-progr.patch 1.36 KB over 1 year ago Download File
0001-Fix-function-prototype-for-TWdialog-user-callback.patch 4.44 KB about 1 month ago Download File
0002-Fix-uninialized-return-value-warning.patch 841 Bytes about 1 month ago Download File
0003-twsc-correct-prototype-for-add_port-declare-prototyp.patch 2.78 KB about 1 month ago Download File
0004-twmc-correct-prototype-for-set_cur_orient-declare-fu.patch 2.56 KB about 1 month ago Download File
graywolf-0.1.6.tar.gz 889 KB about 1 month ago Download File
graywolf.changes 2.95 KB about 1 month ago Download File
graywolf.spec 2.49 KB about 1 month ago Download File

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