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Yosys open synthesis suite

Yosys is a synthesis suite for FPGAs and ASICs.
It includes a verilog parser and the logic synthetizer ABC.

Source Files (show merged sources derived from linked package)

Filename Size Changed Actions
0001-Avoid-symbol-reference-from-library-to-hosting-progr.patch 1.36 KB about 1 year ago Download File
0001-cfree-has-been-removed-from-glibc-2.26.patch 562 Bytes 4 months ago Download File
0002-Use-CMAKE_INSTALL_LIBDIR-instead-of-CMAKE_INSTALL_PR.patch 6.02 KB about 1 year ago Download File
0003-Fix-no-return-in-nonvoid-function-warnings.patch 262 KB 3 months ago Download File
0004-Add-missing-includes-to-have-correct-prototypes.patch 4.25 KB 4 months ago Download File
0005-Add-headers-for-prototypes.patch 9.63 KB 4 months ago Download File
0006-Miscellaneous-return-value-fixes.patch 3.55 KB 4 months ago Download File
0007-Fix-bad-cast-int-vs-int.patch 1.36 KB 4 months ago Download File
0008-Fix-linking-during-parallel-build.patch 5.52 KB about 1 year ago Download File
graywolf-0.1.4.tar.gz 798 KB about 1 year ago Download File
graywolf.changes 1.96 KB 3 months ago Download File
graywolf.spec 2.94 KB 4 months ago Download File

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