verilator
Verilator is the fastest free Verilog HDL simulator, and beats most commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams.
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osc -A https://api.opensuse.org checkout home:dirkmueller:Factory/verilator && cd $_
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Source Files (show merged sources derived from linked package)
Filename | Size | Changed |
---|---|---|
_link | 0000000119 119 Bytes | |
verilator-4.228.tar.gz | 0002623600 2.5 MB | |
verilator.changes | 0000008054 7.87 KB | |
verilator.spec | 0000003260 3.18 KB |
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