OpenVAF is a Verilog-A compiler that can compile Verilog-A files for use in circuit simulator.
The major aim of this Project is to provide a high-quality standard compliant compiler for Verilog-A.
Furthermore, the project aims to bring modern compiler construction algorithms/data structures to a field with a lack of such tooling.

Some highlights of OpenVAF include:

* **fast compile** times (usually below 1 second for most compact models)
* high-quality **user interface**
* **easy setup** (no runtime dependencies even for cross compilation)
* **fast simulations** surpassing existing solutions by 30%-60%, often matching handwritten models
* IDE aware design