STATIC TIMING ANALYSIS
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The advent of semiconductor fabrication technologies now allows high
performance in complex integrated circuits.

With the increasing complexity of these circuits, static timing analysis (STA)
has revealed itself as the only feasible method ensuring that expected
performances are actually obtained.

In addition, signal integrity (SI) issues due to crosstalk play a crucial role
in performance and reliability of these systems, and must be taken into account
during the timing analysis.

However, performance achievement not only lies in fabrication technologies,
but also in the way circuits are designed. Very high performance designs are
obtained with semi or full-custom designs techniques.

The HITAS platform provides advanced STA and SI solutions at transistor level.
It has been built-up in order to allow engineers to ensure complete timing and
SI coverage on their digital custom designs, as well as IP-reuse through timing
abstraction.

Furthermore, hierarchy handling through transparent timing views allows
full-chip verification, with virtually no limit of capacity in design size.