File vhd2vl.spec of Package vhd2vl

#
# spec file for package vhd2vl
#
# Copyright (c) 2015 SUSE LINUX GmbH, Nuernberg, Germany.
#
# All modifications and additions to the file contributed by third parties
# remain the property of their copyright owners, unless otherwise agreed
# upon. The license for this file, and modifications and additions to the
# file, is the same license as for the pristine package itself (unless the
# license for the pristine package is not an Open Source License, in which
# case the license is the MIT License). An "Open Source License" is a
# license that conforms to the Open Source Definition (Version 1.9)
# published by the Open Source Initiative.

# Please submit bugfixes or comments via http://bugs.opensuse.org/
#

Name:           vhd2vl
Version:	2.5
Release:	2.5
License:	GPL-2.0
Summary:	VHDL to Verilog converter
Url:		http://doolittle.icarus.com/~larry/vhd2vl
Group:		Applications/Engineering
Source:		http://doolittle.icarus.com/~larry/vhd2vl/vhd2vl-2.5.tar.gz
BuildRequires:	gcc
BuildRequires:	flex
BuildRequires:	bison
BuildRoot:      %{_tmppath}/%{name}-%{version}-build

%description
Vhd2vl is designed to translate synthesizable VHDL into Verilog 2001.
It does not support the full VHDL grammar - most of the testbench
related features have been left out.  See the examples and
translated_examples directories for examples of what vhd2vl can do.

%prep
%setup -q

%build
cd src
make %{?_smp_mflags}

%install
mkdir -p %{buildroot}%{_bindir}
mkdir -p %{buildroot}%{_datadir}/%{name}
mv src/vhd2vl %{buildroot}%{_bindir}
mv examples %{buildroot}%{_datadir}/%{name}
mv translated_examples %{buildroot}%{_datadir}/%{name}

%post

%postun

%files
%defattr(-,root,root)
%doc changes GPLv2.txt README.txt
%{_datadir}/*
%{_bindir}/*