VHDL to Verilog converter
http://doolittle.icarus.com/~larry/vhd2vl
Vhd2vl is designed to translate synthesizable VHDL into Verilog 2001.
It does not support the full VHDL grammar - most of the testbench
related features have been left out. See the examples and
translated_examples directories for examples of what vhd2vl can do.
- Download package
-
Checkout Package
osc -A https://api.opensuse.org checkout electronics/vhd2vl && cd $_ - Create Badge
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Source Files
| Filename | Size | Changed |
|---|---|---|
| vhd2vl-2.5.tar.gz | 0000046240 45.2 KB | |
| vhd2vl.spec | 0000001740 1.7 KB |
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