File yosys.changes of Package yosys
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Fri Sep 5 20:44:03 UTC 2025 - Wojciech Kazubski <wk@ire.pw.edu.pl>
- Update to version 0.57
* New commands and options
+ Added "-initstates" option to "abstract" pass.
+ Added "-set-assumes" option to "equiv_induct" and
"equiv_simple" passes.
+ Added "-always" option to "raise_error" pass.
+ Added "-hierarchy" option to "stat" pass.
+ Added "-noflatten" option to "synth_quicklogic" pass.
* Various
+ smtbmc: Support skipping steps in cover mode.
+ write_btor: support $buf.
+ read_verilog: support package import.
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Mon Aug 18 19:20:02 UTC 2025 - Wojciech Kazubski <wk@ire.pw.edu.pl>
- Update to version 0.56
* New commands and options
+ Added "-unescape" option to "rename" pass.
+ Added "-assert2cover" option to "chformal" pass.
+ Added "linecoverage" pass to generate lcov report from selection.
+ Added "opt_hier" pass to enable hierarchical optimization.
+ Added "-hieropt" option to "synth" pass.
+ Added "-expect-return", "-err-grep" and "-suffix" options
to "bugpoint" pass.
+ Added "raise_error" dev pass.
* Various
+ Added groups to command reference documentation.
+ Added bugpoint guide to documentation.
+ verific: correctly reset Verific flags after import.
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Tue Jul 8 22:11:42 UTC 2025 - Wojciech Kazubski <wk@ire.pw.edu.pl>
- Update to version 0.55
* Various
+ read_verilog: Implemented SystemVerilog unique/priority if.
+ "attrmap" pass is able to alter memory attributes.
+ verific: Support SVA followed-by operator in cover mode
- Patch yosys-use-system-cxxopts.patch rebased
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Sun Jun 22 08:29:05 UTC 2025 - Wojciech Kazubski <wk@ire.pw.edu.pl>
- Update to version 0.54
* New commands and options
+ Added "-genlib" option to "abc_new" and "abc9_exe" passes.
+ Added "-verbose" and "-quiet" options to "libcache" pass.
+ Added "-no-sort" option to "write_aiger" pass.
* Various
+ Added "muldiv_c" peepopt.
+ Accept (and ignore) SystemVerilog unique/priority if.
+ "read_verilog" copy inout ports in and out of functions/tasks.
+ nable single-bit vector wires in RTLIL.
* Xilinx support
+ Single-port URAM mapping to support memories 2048 x 144b
- Patch yosys-use-python311.patch rebased
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Thu May 22 17:02:28 UTC 2025 - Wojciech Kazubski <wk@ire.pw.edu.pl>
- Update to version 0.53
* New commands and options
+ Added "constmap" pass for technology mapping of coarse
constant value.
+ Added "timeest" pass to estimate the critical path in clock
domain.
+ Added "-blackbox" option to "cutpoint" pass to cut all
instances of blackboxes.
+ Added "-noscopeinfo" option to "cutpoint" pass.
+ Added "-nocleanup" option to "flatten" pass to prevent
removal of unused submodules.
+ Added "-declockgate" option to "formalff" pass that turns
clock gating into clock enables.
* Various
+ Added "$scopeinfo" cells to preserve information during
"cutpoint" pass.
+ Added dataflow tracking documentation.
+ share: Restrict activation patterns to potentially relevant
signal.
+ liberty: More robust parsing.
+ verific: bit blast RAM if using mem2reg attribute.
- Patch yosys-use-gcc13.patch rebased
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Fri Apr 11 18:52:07 UTC 2025 - Wojciech Kazubski <wk@ire.pw.edu.pl>
- Update to version 0.52
* New commands and options
+ Added "-pattern-limit" option to "share" pass to limit
analysis effort.
+ Added "libcache" pass to control caching of technology
library data parsed from liberty files.
+ Added "read_verilog_file_list" to parse verilog file list.
* Various
+ Added $macc_v2 cell.
+ Improve lexer performance and zlib support for "read_liberty".
+ opt_expr: optimize pow of 2 cells.
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Wed Mar 12 21:59:39 UTC 2025 - Wojciech Kazubski <wk@ire.pw.edu.pl>
- Update to version 0.51
* New commands and options
+ Added "abstract" pass to allow reducing and never increasing
the constraints on a circuit's behavior in a formal
verification setting.
* Various
+ "splitcells" pass now splits "aldff" cells.
+ FunctionalIR documentation
* QuickLogic support
+ Added IOFF inference for qlf_k6n10f
* Intel support
+ Fixed RAM and DSP support.
+ Overall performance improvement for "synth_intel".
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Wed Feb 12 21:12:58 UTC 2025 - Wojciech Kazubski <wk@ire.pw.edu.pl>
- Update to version 0.50
* Various
+ "write_verilog" emits "$check" cell names as labels.
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Thu Jan 23 00:54:41 UTC 2025 - Wojciech Kazubski <wk@ire.pw.edu.pl>
- Update to version 0.49
* Various
+ "$scopeinfo" cells are now part of JSON export by default.
+ Added option to specify hierarchical separator for "flatten".
+ Improved "wreduce" to handle more cases of operator size reduction.
+ Updated hashing interface, see docs/source/yosys_internals/hashing.rst
for breaking API changes.
* New commands and options
+ Added "-noscopeinfo" option to "json" and "write_json" pass.
- Patch yosys-use-python311.patch rebased
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Sun Dec 15 08:39:24 UTC 2024 - Wojciech Kazubski <wk@ire.pw.edu.pl>
- Update to version 0.48
* Various
+ Removed "read_ilang" deprecated pass.
+ Enhanced boxing features in the experimental "abc_new" command.
+ Added new Tcl methods for design inspection.
+ Added clock enable inference to "dfflibmap".
+ Added a Han-Carlson and Sklansky option for $lcu mapping.
* New commands and options
+ Added "-nopeepopt" option to "clk2fflogic" pass.
+ Added "-liberty" and "-dont_use" options to "clockgate" pass.
+ Added "-ignore_buses" option to "read_liberty" pass.
+ Added "-dont_map" option to "techmap" pass.
+ Added "-selected" option to "write_json" pass.
+ Added "wrapcell" command for creating wrapper modules around
selected cells.
+ Added "portarcs" command for deriving propagation timing arcs.
+ Added "setenv" command for setting environment variables.
* Gowin support
+ Added "-family" option to "synth_gowin" pass.
+ Cell definitions split by family.
* Verific support
+ Improved blackbox support.
- Update to version 0.47
* Various
+ Added cxxopts library for handling command line arguments.
+ Added docs generation from cells help output.
* New commands and options
+ Added "-json" option to "synth_xilinx" pass.
+ Added "-derive_luts" option to "cellmatch" pass.
+ Added "t:@" syntax to "select" pass.
+ Added "-list-mod" option to "select" pass.
+ Removed deprecated "qwp" pass.
* Verific support
+ Initial state handling for VHDL assertions.
- Use python 3.11 and gcc 13 for build for Leap 15.6
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Sat Oct 12 18:41:56 UTC 2024 - Wojciech Kazubski <wk@ire.pw.edu.pl>
- Update to version 0.46
* Various
+ Added new "functional backend" infrastructure with three
example backends (C++, SMTLIB and Rosette).
+ Added new coarse-grain buffer cell type "$buf" to RTLIL.
+ Added "-y" command line option to execute a Python script
with libyosys available as a built-in module.
+ Added support for casting to type in Verilog frontend.
* New commands and options
+ Added "clockgate" pass for automatic clock gating cell
insertion.
+ Added "bufnorm" experimental pass to convert design into
buffered-normalized form.
+ Added experimental "aiger2" and "xaiger2" backends, and an
experimental "abc_new" command
+ Added "-force-detailed-loop-check" option to "check" pass.
+ dded "-unit_delay" option to "read_liberty" pass.
* Verific support
+ Added left and right bound properties to wires when using
specific VHDL types.
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Wed Sep 4 21:15:08 UTC 2024 - Wojciech Kazubski <wk@ire.pw.edu.pl>
- Update to version 0.45
* Various
+ Added cell types help messages.
* New back-ends
+ Added initial NG-Ultra support. ( synth_nanoxplore )
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Sun Aug 11 08:52:06 UTC 2024 - Wojciech Kazubski <wk@ire.pw.edu.pl>
- Update to version 0.44
* Various
+ Added ENABLE_LTO compile option to enable link time
optimizations.
+ Build support for Haiku OS.
* New commands and options
+ Added "keep_hierarchy" pass to add attribute with same name
to modules based on cost.
+ Added options "-noopt","-bloat" and "-check_cost" to
"test_cell" pass.
* New back-ends
Added initial PolarFire support. ( synth_microchip )
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Wed Jul 10 22:22:35 UTC 2024 - Wojciech Kazubski <wk@ire.pw.edu.pl>
- Update to version 0.43
* Various
+ C++ compiler with C++17 support is required.
+ Support for IO liberty files for verification.
+ Limit padding from shiftadd for "peepopt" pass.
* Verific support
+ Support building Yosys with various Verific library
configurations. Can be built now without YosysHQ
specific patch and extension library.
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Tue Jun 11 20:52:10 UTC 2024 - Wojciech Kazubski <wk@ire.pw.edu.pl>
- Update to version 0.42
* New commands and options
+ Added "box_derive" pass to derive box modules.
+ Added option "assert-mod-count" to "select" pass.
+ Added option "-header","-push" and "-pop" to "log" pass.
* Intel support
+ Dropped Quartus support in "synth_intel_alm" pass.
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Wed May 29 20:17:52 UTC 2024 - Wojciech Kazubski <wk@ire.pw.edu.pl>
- Update to version 0.41
* New commands and options
+ Added "cellmatch" pass for picking out standard cells
automatically.
* Various
+ Extended the experimental incremental JSON API to allow
arbitrary smtlib subexpressions.
+ Added support for using ABCs library merging when providing
multiple liberty files.
* Verific support
+ Expose library name as module attribute.
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Thu Apr 11 14:58:14 UTC 2024 - Wojciech Kazubski <wk@ire.pw.edu.pl>
- Update to version 0.40
* New commands and options
+ Added option "-vhdl2019" to "read" and "verific" pass.
* Various
+ Major documentation overhaul.
+ dded port statistics to "stat" command.
+ Added new formatting features to cxxrtl backend.
* Verific support
+ Added better support for VHDL constants import.
+ Added support for VHDL 2009.
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Wed Apr 3 12:21:35 UTC 2024 - Wojciech Kazubski <wk@ire.pw.edu.pl>
- Update to version 0.39
* New commands and options
+ Added option "-extra-map" to "synth" pass.
+ Added option "-dont_use" to "dfflibmap" pass.
+ Added option "-href" to "show" command.
+ Added option "-noscopeinfo" to "flatten" pass.
+ Added option "-scopename" to "flatten" pass.
* SystemVerilog
+ Added support for packed multidimensional arrays.
* Various
+ Added "$scopeinfo" cells to preserve information about
the hierarchy during flattening.
+ Added sequential area output to "stat -liberty".
+ Added ability to record/replay diagnostics in cxxrtl backend.
* Verific support
+ Added attributes to module instantiation.
- Patch fix_clk2fflogic_test.patch removed (applied upstream
-------------------------------------------------------------------
Fri Mar 1 10:41:05 UTC 2024 - Wojciech Kazubski <wk@ire.pw.edu.pl>
- Fix build for Leap 15.x (python >= 3.7 is needed to run tests)
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Mon Feb 26 13:24:11 UTC 2024 - Stefan Brüns <stefan.bruens@rwth-aachen.de>
- Update to version 0.38
See https://github.com/YosysHQ/yosys/releases for details
- Add fix_clk2fflogic_test.patch
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Sat Nov 5 23:16:37 UTC 2022 - Stefan Brüns <stefan.bruens@rwth-aachen.de>
- Update to version 0.22
See https://github.com/YosysHQ/yosys/releases for details
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Sun Dec 20 13:07:20 UTC 2020 - Stefan Brüns <stefan.bruens@rwth-aachen.de>
- Update to version 0.9+git20201222
- Package abc separately (package yosys-abc)
- Move architecture indepedent files to subpackage
- Enable test suite, add patches required to pass
* 0001-Fix-use-after-free-in-LUT-opt-pass.patch
* 0001-ice40-tolerate-unconnected-SB_LUT4-inputs.patch
- Cleanup spec file:
* Fix License tag
* Remove obsolete distro version conditionals
* Remove obsolete constructs
* Move changelog to separate changes file
* Tag license file correctly
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* Tue Dec 22 2015 - David Lanzendörfer <david.lanzendoerfer@o2s.ch>
- switching to GIT
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* Tue Dec 8 2015 - David Lanzendörfer <david.lanzendoerfer@o2s.ch>
- yosys port to openSUSE
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* Mon Apr 6 2015 - Gabriel.Gouvine <gabriel.gouvine_pack@m4x.org>
- Packaged the 0.5 version of yosys
- Do not download ABC through the net but use an archive.
