Yosys open synthesis suite

Edit Package yosys
http://www.clifford.at/yosys/

Yosys is a synthesis suite for FPGAs and ASICs.
It includes a verilog parser and the logic synthetizer ABC.

Source Files
Filename Size Changed
yosys-0.57.tar.gz 0003399252 3.24 MB
yosys-use-gcc13.patch 0000002736 2.67 KB
yosys-use-python311.patch 0000011587 11.3 KB
yosys-use-system-cxxopts.patch 0000000450 450 Bytes
yosys.changes 0000014048 13.7 KB
yosys.spec 0000003352 3.27 KB
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