Yosys open synthesis suite

Edit Package yosys
http://www.clifford.at/yosys/

Yosys is a synthesis suite for FPGAs and ASICs.
It includes a verilog parser and the logic synthetizer ABC.

Source Files
Filename Size Changed
yosys-0.61.tar.gz 0003455431 3.3 MB
yosys-use-gcc13.patch 0000002736 2.67 KB
yosys-use-python311.patch 0000011587 11.3 KB
yosys-use-system-cxxopts.patch 0000000450 450 Bytes
yosys.changes 0000017061 16.7 KB
yosys.spec 0000003352 3.27 KB
Comments 0
No comments available
openSUSE Build Service is sponsored by