Yosys open synthesis suite

Edit Package yosys
http://www.clifford.at/yosys/

Yosys is a synthesis suite for FPGAs and ASICs.
It includes a verilog parser and the logic synthetizer ABC.

Source Files (show merged sources derived from linked package)
Filename Size Changed
fix_clk2fflogic_test.patch 0000002657 2.59 KB
yosys-0.38.tar.gz 0002709217 2.58 MB
yosys.changes 0000001677 1.64 KB
yosys.spec 0000002913 2.84 KB
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