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home:StefanBruens:branches:electronics
graywolf
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Meta Configuration of Package graywolf
<package name="graywolf" project="home:StefanBruens:branches:electronics"> <title>Yosys open synthesis suite</title> <description>Yosys is a synthesis suite for FPGAs and ASICs. It includes a verilog parser and the logic synthetizer ABC. </description> </package>
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