Yosys open synthesis suite
Yosys is a synthesis suite for FPGAs and ASICs.
It includes a verilog parser and the logic synthetizer ABC.
- Links to electronics / graywolf
- Has a link diff
- Download package
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Checkout Package
osc -A https://api.opensuse.org checkout home:StefanBruens:branches:electronics/graywolf && cd $_ - Create Badge
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Source Files (show merged sources derived from linked package)
| Filename | Size | Changed |
|---|---|---|
|
0001-Avoid-symbol-reference-from-library-to-hostin |
0000001395 1.36 KB | |
|
0001-Fix-function-prototype-for-TWdialog-user-call |
0000004547 4.44 KB | |
| 0002-Fix-uninialized-return-value-warning.patch | 0000000841 841 Bytes | |
|
0003-twsc-correct-prototype-for-add_port-declare-p |
0000002843 2.78 KB | |
|
0004-twmc-correct-prototype-for-set_cur_orient-dec |
0000002619 2.56 KB | |
| _link | 0000000119 119 Bytes | |
| graywolf-0.1.6.tar.gz | 0000910767 889 KB | |
| graywolf.changes | 0000003023 2.95 KB | |
| graywolf.spec | 0000002550 2.49 KB |
Latest Revision
buildservice-autocommit
accepted
request 631549
from
Stefan Brüns (StefanBruens)
(revision 18)
Stefan Brüns (StefanBruens)
(revision 18)
baserev update by copy to link target
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