Icarus Verilog
Icarus Verilog is a Verilog compiler that generates a variety of engineering formats, including simulation. It strives to be true to the IEEE-1364 standard.
- Links to windows:mingw:win64 / mingw64-iverilog
- Has a link diff
- Download package
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Checkout Package
osc -A https://api.opensuse.org checkout home:rhabacker:branches:windows:mingw:win64/mingw64-iverilog && cd $_ - Create Badge
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Source Files (show merged sources derived from linked package)
| Filename | Size | Changed |
|---|---|---|
|
0001-vvp-generate-libvvp-import-library-for-MinGW- |
0000001935 1.89 KB | |
| 0002-vvp-install-libvvp-pkg-config-file.patch | 0000002794 2.73 KB | |
| 0003-vvp-create-libvvp-as-versioned-library.patch | 0000002720 2.66 KB | |
| _link | 0000000127 127 Bytes | |
| _service | 0000000636 636 Bytes | |
| mingw64-iverilog.changes | 0000005626 5.49 KB | |
| mingw64-iverilog.spec | 0000003254 3.18 KB | |
| verilog-12.0-install-fixes.patch | 0000013053 12.7 KB |
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