- Update to release 20230406:
* Fixed bug when interpreting leaf 0xb and 0x1f bit widths:
Interpret as bit *offsets*, not *widths* of leaf 4. This fixes off by 1
in (APIC width synth) and incorrectly shifted (APIC synth) PKG_ID & CORE_ID
values.
* For 0xb/*/eax & 0x1f/*/eax, rename field to "bit width of
level & previous levels" to reflect this definition.
* Support APIC bit fields for the newest 4 topology
layers: module, tile, die, die group. And for the mp version, also
the older cu & pkg levels.
* Use the extended APIC ID's when available in a variety of leaves.
* Support leaf 0xb method for AMD/Hygon.
* Added prelim Bergamo A1 stepping from sample from @YuuKi_AnS.
* Added 7/1/edx AMX-COMPLEX instructions.
* Added 7/2/edx UC-lock disable.
* Added 0x10/n/ecx non-contiguous 1s value supported.
* Added 0x1c/ecx event logging supported bitmap.
* Added 0x23/0/ebx decoding.
* Decode 0x80000026/1/ebx core type & native model.
* For 0x80000021/eax, capitalize REP STOSB & REP CMPSB to match
Intel versions in 7/1/eax.
* For 0x80000022/ecx, shorten description, show bitmask only in
hex.
* Update CPUID utility with new feature bits as documented in
the AMD Processor Programming Reference for Family 19h and Model 11h:
0x8000000a/edx extended LVT offset fault change
0x80000021/eax enhanced predictive store forwarding, FSRS, FSRC,
FsGsKernelGsBaseNonSerializing
0x80000022/ebx number of available UMC PMCs
0x80000022/ecx bitmask representing active UMCs