baserev update by copy to link target

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- Add patch use-python3.patch:
  * Use python3 to create header files.

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baserev update by copy to link target

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baserev update by copy to link target

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- Use noun phrase in summary.

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- Update to version 1.30+git.20180323:
  * rename release target to tarball
  * bump minimum for -Werror to gcc 6.3
  * add tag target
  * Make cpuid-freebsd.c:cpuid() handle top word of idx as count (%ecx), same as cpuid-linux.c:cpuid() does.
  * Make native_cpuid() handle top word of idx as count (%ecx), same as cpuid-linux.c:cpuid() does.
  *  Fix vendor/inte/identify-family6-extended.c::get_namestring() to print cpu mode name correcty. When I tested on Kaby Lake machine, it shows:
  * amd: Identify Family 17h model CPUs
  * Makefile: Use pkg-config libpci location
- Use more accurate versioning
- Update build requirements
- Make building more verbose

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baserev update by copy to link target

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- Update to HEAD (9501749231164135db25c72cbeb42bf32af1519b)
  * Make it possible to statically link with libpci.
  * Add another Nehalem variant
  * Add exact steppings and complete list of all bloomfield cores.
  * add Knights Mill Xeon Phi.
  * - Add PREFETCHW instruction flag.
    - Add Hardware Duty Cycling flag.
    - Add HW-controlled performance states (HWP) flags.
  * Add 0x64, 0xa0, 0xc3 and 0xc4 into DTLB_cache_table[].
  * - Add Atom E3500.
    - Add Atom X3-C3000 [Silvermont].
  *  Add NetBSD support. Note that NetBSD has not API to access MSR register from userland.
  * handle null EBDA pointer.
  * handle failure from enumerate_cpus

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baserev update by copy to link target

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- Update to 1.30
  * no upstream changelog available
- Cleanup spec file with spec-clener

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baserev update by copy to link target

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- Use parallel build and remove ancient specfile tags and sections

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baserev update by copy to link target

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- Update to latest git version
   -> 1.29 plus some more patches until
      git commit aa57556f60c89eb84f65cb55e0215ff9be97dbec
  Includes:
     - Show boost state info on AMD
     - Identify some more cpus
     - ...

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baserev update by copy to link target

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- Update to version 1.28
  Changelog (extracted git commit subjects, shortened):
    Some more IDA decoding
    Start decoding IDA
    gather topology info per-cpu
    Split intel info into basic/extended.
    only display extended family/model if set
       print out the BIOS programmed string by default too.
       Also clarify which is x86info's guess.
    put back some of the mptable verbose/silent code.
    rename bluesmoke to machine_check
    Split MSR-PM into thermal and performance
    IA32_PERF_STATUS is model specific.
    Dump APIC registers
    Add and show info about virtual and physical address sizes
    Decode MTRRphysBase and MTRRphysMask
    use MB macro, like in the kernel
    update cache descriptors
    Decode MTRRcap and MTRRdefType registers
    Make makenodes script more robust
    Add an Atom variant
    Add an Intel codename.
    Add an atom ident.
    Add some Nehalem core codenames.
    Add Core i7 informational URL.
    Report whether longnops are supported
  Changelog (extracted git commit subjects from 1.25-1.27):
    only support topology parsing on intel for now
    Factor out the topology printing code into its own routine

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- Update to version 1.27
  No changelog found, git history can be found here:
  http://git.choralone.org/?p=x86info.git;a=shortlog

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checked in (request 35125)

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