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Revisions of cpuid

buildservice-autocommit accepted request 1094829 from Jan Engelhardt's avatar Jan Engelhardt (jengelh) (revision 50) 
baserev update by copy to link target
Jan Engelhardt's avatar Jan Engelhardt (jengelh) committed (revision 49) 
Curate changelog
Jan Engelhardt's avatar Jan Engelhardt (jengelh) accepted request 1094333 from Valentin Lefebvre's avatar Valentin Lefebvre (vlefebvre) (revision 48) 
Update to release 20230614
buildservice-autocommit accepted request 1079429 from Jan Engelhardt's avatar Jan Engelhardt (jengelh) (revision 47) 
baserev update by copy to link target
Jan Engelhardt's avatar Jan Engelhardt (jengelh) committed (revision 46) 
trim changelog to size
Jan Engelhardt's avatar Jan Engelhardt (jengelh) accepted request 1079377 from Egbert Eich's avatar Egbert Eich (eeich) (revision 45) 
- Update to release 20230406:
  * Fixed bug when interpreting leaf 0xb and 0x1f bit widths:
    Interpret as bit *offsets*, not *widths* of leaf 4. This fixes off by 1
    in (APIC width synth) and incorrectly shifted (APIC synth) PKG_ID & CORE_ID
    values.
  * For 0xb/*/eax & 0x1f/*/eax, rename field to "bit width of
    level & previous levels" to reflect this definition.
  * Support APIC bit fields for the newest 4 topology
    layers: module, tile, die, die group.  And for the mp version, also
    the older cu & pkg levels.
  * Use the extended APIC ID's when available in a variety of leaves.
  * Support leaf 0xb method for AMD/Hygon.
  * Added prelim Bergamo A1 stepping from sample from @YuuKi_AnS.
  * Added 7/1/edx AMX-COMPLEX instructions.
  * Added 7/2/edx UC-lock disable.
  * Added 0x10/n/ecx non-contiguous 1s value supported.
  * Added 0x1c/ecx event logging supported bitmap.
  * Added 0x23/0/ebx decoding.
  * Decode 0x80000026/1/ebx core type & native model.
  * For 0x80000021/eax, capitalize REP STOSB & REP CMPSB to match
    Intel versions in 7/1/eax.
  * For 0x80000022/ecx, shorten description, show bitmask only in
    hex.
  * Update CPUID utility with new feature bits as documented in
    the AMD Processor Programming Reference for Family 19h and Model 11h:
    0x8000000a/edx extended LVT offset fault change
    0x80000021/eax enhanced predictive store forwarding, FSRS, FSRC,
    FsGsKernelGsBaseNonSerializing
    0x80000022/ebx number of available UMC PMCs
    0x80000022/ecx bitmask representing active UMCs
buildservice-autocommit accepted request 1064049 from Jan Engelhardt's avatar Jan Engelhardt (jengelh) (revision 44) 
baserev update by copy to link target
Jan Engelhardt's avatar Jan Engelhardt (jengelh) accepted request 1064033 from Dirk Mueller's avatar Dirk Mueller (dirkmueller) (revision 43) 
- updaet to 20230120:
  * Intel's 13th Generation Core datasheet provides stepping names as
    well as numbers!  So:
  * cpuid.c: Added synth decoding for (0,6),(11,7) Raptor Lake B0 stepping.
  * cpuid.c: Added synth decoding for (0,6),(11,15) Raptor Lake C0
    steppings, and clarified case for unknown stepping.
  * cpuid.man: Added 743844: 13th Generation Core datasheet.
  * cpuid.c: Fixed (0,6)(12,15) synth typo: Emearld Rapids.
  * cpuid.c: Added 6/eax IA32_HW_FEEDBACK_THREAD_CONFIG bit 25.
  * cpuid.c: Added 7/0/edx SGX-KEYS: SGX attestation services.
  * cpuid.c: Clarified 7/0/edx IA32_MCU_OPT_CTRL SRBDS mitigation MSR.
  * cpuid.c: Clarified 7/0/edx IA32_TSX_FORCE_ABORT MSR.
  * cpuid.c: Added 7/1/edx CET_SSS: shadow stacks w/o page faults.
  * cpuid.c: Added several 7/2/edx bits.
  * cpuid.c: In 0xd/0/eax, corrected CET_U & CET_S, which were IA32_XSS.
  * cpuid.c: In 0xd/0/eax, removed the IA32_XSS bits, which aren't
    relevant for XCR0.
  * cpuid.c: For 0xd/1/ecx, enumerate the IA32_XSS bits instead of a
    hex bitmask.
  * cpuid.c: For 0xd, added IA32_XSS PASID state (couple places).
  * cpuid.c: Renamed 0x1a: Native Model ID.
  * cpuid.c: Added synth & uarch decoding for (0,6),(11,15) Raptor Lake
    from MSR_CPUID_table*.
  * cpuid.c: Added synth decoding for (0,6),(9,7),5 Pentium Gold G7400,
    based on instlatx64 sample.
  * cpuid.c: Added rudimentary synth decoding for future (0,6),(12,15)
    Emerald Rapids CPUs.
  * cpuid.c: Added 7/1/eax LASS: linear address space separation.
  * cpuid.c: Corrected 0x18/n/edx maximum number of addressible IDs, which
    should use minus-one notation.
buildservice-autocommit accepted request 1040214 from Jan Engelhardt's avatar Jan Engelhardt (jengelh) (revision 42) 
baserev update by copy to link target
Jan Engelhardt's avatar Jan Engelhardt (jengelh) committed (revision 41) 
stick to required changelog syntax
Jan Engelhardt's avatar Jan Engelhardt (jengelh) accepted request 1040204 from Valentin Lefebvre's avatar Valentin Lefebvre (vlefebvre) (revision 40) 
- Update to release 20221201
  * Clarified synth decoding for Intel Xeon D-1700.
  * Added uarch & synth decoding for AMD 4800S Desktop Kit, based on
    instlatx64 sample.
  * Added uarch decoding for AMD Genoa A1, based on instlatx64 sample
  * Added uarch decoding for (0,6),(12,15) Emerald Rapids, from LX*.
  * Added synth & uarch decoding for (10,15),(10,1) Bergamo.
	* Added 0x8000000a/edx bits: ROGPT, VNMI, IBS virtualization.
	* Added 0x8000001b/eax bit: IBS L3 miss filtering support.
	* Added 0x8000001f/eax bits: RMPQUERY instruction support,
	  VMPL supervisor shadow stack support, VMGEXIT parameter support,
	  virtual TOM MSR support, IBS virtual support for SEV-ES guests,
	  SMT protection support, SVSM communication page MSR support,
	  VIRT_RMPUPDATE & VIRT_PSMASH MSR support.
	* Added 0x80000020/0/ecx bit: L3 range reservation support.
	* Added 0x80000021/eax bits: automatic IBRS,
	  CPUID disable for non-privileged.
	* Added 0x80000022/eax bit: AMD LBR & PMC freezing.
	* Added 0x80000022/ebx field: number of LBR stack entries.
	* Added 0x80000023 leaf: Multi-Key Encrypted Memory Capabilities.
	* Added 0x80000026 leaf: AMD Extended CPU Topology.
	* cpuid.c: use lseek64 and cpuset_setaffinity, Added 0x80000022/eax
    AMD LBR V2 flag, from LX*.
buildservice-autocommit accepted request 1010511 from Jan Engelhardt's avatar Jan Engelhardt (jengelh) (revision 39) 
baserev update by copy to link target
Jan Engelhardt's avatar Jan Engelhardt (jengelh) committed (revision 38) 
wrap changelog
modern macros
Jan Engelhardt's avatar Jan Engelhardt (jengelh) accepted request 1010493 from Valentin Lefebvre's avatar Valentin Lefebvre (vlefebvre) (revision 37) 
- Update to release 20221003
  * Added synth decoding for AMD Ryzen (Phoenix E0, Storm Peak A1)
  * Added synth & uarch synth decoding for
    * (0,6),(11,5) Intel Meteor Lake
    * (0,6),(11,6) Intel Grand Ridge (Crestmont)
    * (0,6),(11,14) Intel Granite Rapids
  * Renamed 7/0/eax enh hardware feedback to simply Thread Director.
  * Added 7/1/eax instructions ... 
  * Added 0x12/0/eax SGX ENCLU EDECCSA flag.
  * Added 0x23 Architecture Performance Monitoring Extended leaf decoding.
  * Corrected AVX512IFMA description: integer FMA, not just FMA.
- Release 20220927
  * Added synth decoding for (10,15),(6,1) Raphael
  * Fixed missing return statement in get_nr_cpu_ids()'s default case, 
    used by Cygwin.
  * Fixed title for AMD 0x8000001a leaf: Performance Optimization identifiers.
  [cpuid-20221003.src.tar.gz]
buildservice-autocommit accepted request 994880 from Jan Engelhardt's avatar Jan Engelhardt (jengelh) (revision 36) 
baserev update by copy to link target
Jan Engelhardt's avatar Jan Engelhardt (jengelh) committed (revision 35) 
- Update to release 20220812
Jan Engelhardt's avatar Jan Engelhardt (jengelh) committed (revision 33)
buildservice-autocommit accepted request 840201 from Jan Engelhardt's avatar Jan Engelhardt (jengelh) (revision 31) 
baserev update by copy to link target
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